Valley Design Techniques Outperform Peak Current-Mode Approach for CPU Supplies

Jul 1, 2001 12:00 PM
By Nazzareno Rossetti, Fairchild Semiconductor, and Seth R. Sanders, University of California

Valley current-mode control buck architecture employs leading-edge modulation.

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Modern CPUs require supply voltages of 1.5V and below and currents of up to 100A. This power frequently originates from the 12V output of a “silver box” power supply. Developing the lower voltage requires a buck converter operating at duty cycles of about 10%, stretching the performance limits of conventional current-mode control architectures. Valley current-mode allows the buck converter to meet and exceed those specifications.

To understand the valley current-mode control, we first have to look at traditional peak current-mode control in Fig. 1(a), which is based on trailing-edge modulation. In closed-loop operation, the error amplifier forces V_OUT to equal V_REF. At the error amplifier's output, its output voltage V_ε is compared with the product of the high-side MOSFET's current (I_L) times R_DS(on). When I_L×R_DS(on) exceeds the error voltage, the PWM comparator goes high. This resets the flip-flop, terminating the charge phase by turning off the high-side driver and initiating the discharge phase by turning on the low-side driver. The discharge phase continues until the next clock pulse that sets the flip-flop and initiates a new charging phase.

Fig. 1(b) illustrates valley current-mode control based on leading-edge modulation. The error amplifier again forces V_OUT to equal V_REF at its input. But now its output voltage, V_ε, is compared with the low-side MOSFET's current (I_L) times R_DS(on). When I_L×R_DS(on) falls below the error voltage the PWM comparator goes high. This sets the flip-flop, initiating the charge phase by turning on the high-side driver and terminating the discharge phase by turning off the low-side driver. The charge phase continues until the next clock pulse resets the flip-flop, initiating a new discharge phase.

Current Sensing

“Lossless” current sensing employs no discrete sense resistor, sensing instead the voltage across the low-side MOSFET which is ON normally for 90% of the time. Because the ON time of the low-side MOSFET is almost 10 times longer than that of the high-side MOSFET, sampling and processing of the low-side device's current is much easier.

Sensing of the high-side current at low duty cycles is so difficult that some designs have been based on sensing low-side current and trailing-edge current control. However, the current information obtained this way comes after the current has peaked and has started the decaying phase allowing only cycle-by-cycle peak-current control during the next cycle. This means you hold the sampled information until the next cycle. A sample-and-hold mechanism adds complexity and a delay or phase shift, which can compromise the control loop's stability.

For valley or peak current-mode control, in the case of very low duty cycle operation, the minimum possible ON time of the high-side driver limits the maximum frequency of operation. In both cases you determine the high-side driver's minimum pulse width by the same set of initial physical limitations, and the peak current-mode control's maximum frequency is limited by a settling-time requirement. The pulse must be wide enough to allow you to measure the current. This limitation applies to both lossless high-side sensing and to sensing with a discrete high-side sense resistor.

Peak Current-Mode Control

For peak current-mode control:

T_MINP=T_ONP-MIN/DC (1)

Where:

T_MINP=Minimum period of operation in peak current-mode control

T_ONP-MIN=Settling time for sensing the high-side current

DC=Duty Cycle

If T_ONP-MIN=100 ns and DC=0.1:

T_MINP=100 ns/0.1=1 µs

And:

f_MAXP=1/T_MINP (2)

Where:

f_MAXP=Maximum operating frequency in peak current-mode control

f_MAXP=1 MHz

Valley Current-Mode Control

In valley current-mode control where the low-side current is sampled, the limitation discussed above is far less strict. T_MINV=T_ONV-MIN/(1-DC) (3)

Where:

T_MINV=Minimum operating period in valley current-mode control based on low-side minimum pulse width.

T_ONV-MIN=Settling time for sensing the low-side current

If T_ONV-MIN=100 ns and DC=0.1:

T_MINV=100 ns/(1-0.1)=110 ns

And: f_MAXV=1/T_MINV (4)

Where:

f_MAXV=Maximum operating frequency

f_MAXV=1/110 ns=9 MHz

The converter still has to meet the constraint of minimum ON time of the high-side driver. Transition times of 10 ns and below are obtainable today.

Therefore:

T_ONHV-MIN=T_R+T_F (5)

Where:

T_ONHV-MIN=Minimum ON time of the high side device

T_R=Rise time in nanoseconds

T_F=Fall time in nanoseconds

T_ONHV-MIN=10+10=20 ns

Also:

T_MINHV=T_ONHV-MIN/DC (6)

Where:

T_MINHV=Minimum operating period in valley current-mode control based on high side minimum pulse width.

T_MINHV=20 ns/0.1=200 ns

And:

f_MAXHV=1/T_MINHV (7)

f_MAXHV=Maximum operating frequency in valley current-mode control based on high side minimum pulse width.

f_MAXHV=1/T_MINHV=5 MHz

The most severe constraint is the high side minimum pulse width, which for valley current-mode control still translates into a high maximum clock frequency (f_MAXHV) of operation.

Conventional monolithic and discrete technologies don't permit practical operation at such a high clock rate. As these technologies improve, only valley current mode control will operate at such high frequencies.

Transient Response

The advantage of valley control is obvious in Fig. 2, on page 51. It can turn on immediately in response to a step current as opposed to peak control where a delay (T_DELAY) as high as a full clock period is to be expected. Both cases show the inductor current ramps up with a slope determined by the inductance and saturated voltage appearing across the inductor, limited by the maximum duty cycle DC_MAX.

If the clock is 700 kHz per phase, a full period delay corresponds to 1.5 ms. A traditional peak current-mode control architecture needs enough output capacitance to hold up for an extra 1.5 ms compared with valley current-mode control. Consider that a 1 µF output capacitor will discharge an extra 100mV with a 65A load in 1.5 µs.

Fig. 3, on page 51, illustrates the comparative responses to a negative load current step. During a negative load-current step, the valley control scheme responds with zero delay. With peak current-mode control, after each clock pulse, the controller forces a minimal width high-side ON time. The speed of the current control loop determines minimal ON time. The valley control scheme offers superior transient response with a negative load step.

Valley Control IC

The FAN5093 is a 2-phase interleaved buck controller IC implementing valley control architecture based on leading-edge modulation. The current is normally sensed across the low-side MOSFET's R_DS(on) (for lossless current sensing). For precision applications, you can place a physical sense resistor in series with the source of the low-side MOSFET.

Looking at Fig. 4, on page 52, you can see the response of the two PWM switching nodes of the 2-phase interleaved buck converter, with the FAN5093 clocking each phase at a frequency of 700 kHz.

Fig. 5, on page 55, is the response of the voltage regulator to a 25A per phase positive current step. You can see the response of the voltage regulator to a 25A per phase negative current step in Fig. 6.

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