SPICE Model Supports LDO Regulator Designs

May 1, 2005 12:00 PM
By Steven Sandler, Program Engineer, Acme Electric, Aerospace Division an Actuant Co., Tempe, Ariz., and Charles E. Hymowitz, Managing Director, AEI Systems, Los Angeles, Calif.

SPICE models of power MOSFETs may prove inadequate in applications such as lowdropout regulator designs.

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During a recent design of a low-dropout voltage regulator (LDO) using a power MOSFET as the series pass element, it became clear that there are basic inadequacies in many of the MOSFET SPICE models provided by the MOSFET manufacturers and included in the EDA vendors' SPICE model libraries. This article identifies these shortcomings and defines an improved SPICE model. The new model is used to simulate results, which are then compared with measurements made from a prototype built for that purpose.

In the great majority of applications, MOSFETs are used as switching devices. When used in switching applications, the characteristics that are of the greatest interest are R_DS(ON), capacitance and gate charge. R_DS(ON) represents the conduction loss, while the capacitance and gate charge determine the major contributions to the switching loss. There is generally less interest among design engineers in the transfer characteristic, I_DRAIN versus V_GATE and its derivative, transconductance (G_FS). In fact, most MOSFET data sheets only provide G_FS at a single operating point, and it is normally specified only as a minimum value. In the switching application, it is important to know the gate voltage for a given drain current, because that information is partly responsible for the gate current and, therefore, the switching speed. However, transconductance is generally not a significant characteristic in the application as a switch.

Table 1. Measured versus SPICE model values for International Rectifier's IRHF57230 MOSFET.

	Measured Results			Manufacturer Model Results			Proposed Model Results
ID (mA)	VGS (V)	REFF (V)	GFS (S)	VGS (V)	REFF (V)	GFS (S)	VGS (V)	Error
1	3.25	148.784	0.007	4.44	1.000	1.000	3.22	-0.93%
2	3.34	77.234	0.013	4.44	0.645	1.550	3.33	-0.30%
5	3.45	36.653	0.027	4.45	0.447	2.237	3.46	0.29%
10	3.57	17.257	0.058	4.45	0.351	2.849	3.57	0.00%
25	3.70	7.3570	0.136	4.45	0.261	3.831	3.72	0.54%
50	3.82	3.6210	0.276	4.46	0.221	4.525	3.83	0.26%
100	3.93	1.7990	0.556	4.46	0.190	5.263	3.95	0.51%
200	4.03	0.9400	1.064	4.49	0.168	5.952	4.08	1.23%
500	4.15	0.4490	2.228	4.53	0.149	6.711	4.28	0.70%
							Mean Difference	0.25%

Nevertheless, transconductance is of primary importance in the development of an LDO MOSFET voltage regulator because the effects of G_FS are seen as the output resistance of the MOSFET. The effects of this resistance present several concerns:

• The resistance is the open-loop output impedance of the regulator, which we would ideally like to be zero.

• The resistance is nonlinearly dependent on the drain current of the MOSFET.

• The resistance forms a pole with the output capacitor, which is also dependent on drain current, and must be accounted for in the design of the feedback system.

The SPICE MOSFET Model

The SPICE template for a small-signal MOSFET is fixed within the program code as a primitive element. While the primitive element alone cannot be used to effectively model the nonlinearities of a power MOSFET, a level 1 or level 3 MOSFET model is still at the core of most power MOSFET subcircuits. The basic SPICE expression for the MOSFET drain current, as a function of gate voltage, is defined as:

I_D=(V_GS-V_TO)² · K_P · (1-λ) (Eq. 1)

Where V_GS is the MOSFET gate voltage, V_TO is the MOSFET threshold voltage, K_P is a constant, defining the “gain” of the MOSFET, and λ refers to the slope of I_D versus drain voltage.

Differentiating this equation with respect to V_GS results in:

G_FS=2 · (V_GS-V_TO) · K_P · (1-λ) (Eq. 2)

During the development of the MOSFET regulator prototype, measurements were made of the drain current versus the gate voltage, as well as direct measurement of G_FS. Direct measurement of G_FS was accomplished using an HP3577A network analyzer to measure the corner frequency, with a fixed output capacitor as a function of drain current. In a similar fashion, the HP3577A network analyzer was used to measure the pole created by an input resistor and the device capacitance, in order to determine the input capacitance (C_ISS) and output capacitance (C_OSS) of the device as a function of drain voltage.

The MOSFET used in this example is an IRHF57230, a radiation tolerant, R5 process device manufactured by International Rectifier (El Segundo, Calif.). Many devices from other manufacturers also were measured for comparison. This article concentrates only on the IRHF57230.

Table 1 shows the results of measurements along with the results of the manufacturers' SPICE model for V_GS, the effective source resistance (R_EFF or 1/G_FS) and G_FS as a function of drain current. For convenience, Table 1 also includes the V_GS simulation results from the proposed model and the error between the measured results and the proposed model.

The results of the measurements for the MOSFET were surprising in that they do not fit the primitive element for the SPICE MOSFET model. It also is surprising to see the large discrepancy between the measured results and the manufacturer's SPICE model for the device, which were posted on its website. Inspecting this data, it becomes obvious that the resistance of the MOSFET (1/G_FS) is inversely proportional to the drain current, which is the basic characteristic of a silicon diode.

A new SPICE model was constructed using a topology that would provide the correct results for G_FS and, therefore, for R_EFF. It also incorporates R_DS(ON) (including temperature), capacitance and the drain-source body diode (Fig. 1).

The Mathcad Minerr function was used to best fit the data, using the following relationship:

Where I_S and N are the characteristics of diode, D₁, and V_TO is the threshold voltage of MOSFET M1. The K_P of M1 is considered to be infinite and, in this example, is set to 1000. The remaining parameters, including the junction capacitance, body diode and temperature characteristics are modeled using previously developed techniques^{[1, 2, 3]}.

The complete SPICE subcircuit is shown in the following listings:

.SUBCKT AEi57230 1 8 90

* D G S

* This model accounts for nonlinear capacitance and temperature characteristics.

* Transconductance has been verified from 1 mA to 9 A and at 125°C.

* Capacitances are assumed to be constant over temperature.

* Some simulators may not accept M > 2 or the M=2.065 used here.

* Setting M = 2 is acceptable.

* Does not include package-related lead inductance.

.MODEL NMOD NMOS (VTO=2.14 KP=1000)

.MODEL RDS RES (TC1=7.5M TC2=21.2U); an additional data point at -55°C is desired

.MODEL RDS2 RES (TC1=4M); an additional data point at -55°C is desired

.MODEL DMOD D (N=11 IS=100U EG=2.55)

.MODEL DBODY D (CJO =830P VJ=4.95 M=1.21 IS=1.134P N=.999 RS=.073)

.MODEL DMOD3 D (CJO=754P VJ=9.523 M=2.065)

.MODEL DMOD2 D (CJO=10N)

RS 4 90 RDS2 0.04

VSNS 3 4

D1 7 2 DMOD

* F1 7 2 VSNS -1

* Some simulators prefer the syntax in F1 or “B1 2 7 I=ABS(I(VSNS))” in place of GB1

GB1 2 7 Value={ ABS(I(VSNS)) }

RBULK 7 8 1

RD 1 10 RDS 0.125

D2 3 10 DBODY

D3 6 7 DMOD2

D4 6 10 DMOD3

CGD 7 10 92P

CGS 7 90 1N

M1 10 2 3 3 NMOD

.ENDS

The subcircuit model represents the following performance characteristics:

Gate transfer (V_GS versus I_D) including temperature

C_ISS, C_RSS and C_OSS including nonlinearity

G_FS including low current performance

R_DS(ON) including temperature

Body diode forward-voltage characteristics.

The model is designed to be used with and has been tested with IsSPICE, Microcap V and PSPICE simulators. (This model was developed by: AEI Systems LLC [aeng.com]. Copyright 1999, all rights reserved. This model is subject to change without notice. Users may not directly or indirectly resell or redistribute this model.)

Table 2. Junction capacitance values from the SPICE model of IRHF57230.

VDS (V)	CISS (F)			CGD (F)			COSS (F)
	Measured	Simulated	Error	Measured	Simulated	Error	Measured	Simulated	Error
0	1.85E-09	1.82E-09	-1.89%	8.45E-10	8.53E-10	0.95%	1.68E-09	1.61E-09	-3.94%
5	1.41E-09	1.44E-09	1.66%	4.04E-10	4.12E-10	1.99%	7.2E-10	7.69E-10	6.77%
10	1.28E-09	1.29E-09	0.80%	2.71E-10	2.79E-10	2.97%	5.58E-10	4.9E-10	-12.30%
25	1.14E-09	1.14E-09	-0.09%	1.37E-10	1.45E-10	5.88%	1.98E-10	2.44E-10	23.36%
50	1.12E-09	1.11E-09	-0.56%	1.13E-10	1.21E-10	7.11%	1.43E-10	1.58E-10	9.90%
	Mean Error		-0.02%	Mean Error		3.78%	Mean Error		4.76%

The simulation results for the proposed model are shown in Figs. 2, 3 and 4. Fig. 2 shows the gate-transfer function at room temperature and at high temperature. Fig. 3 shows both the simulated and the measured results of G_FS as a function of current, and Fig. 4 shows the simulated result of R_DS(ON) as a function of temperature. Meanwhile, Tables 2 and 3 compare measured results versus SPICE simulated results for junction capacitance and transconductance, respectively. Comparisons with the MOSFET manufacturer's data can be made by accessing the IRHF57230 data sheet at www.irf.com.

The LDO Regulator Design

A SPICE representation of the completed LDO regulator using this new subcircuit demonstrates the performance of the MOSFET model shown in Fig. 5.

Table 3. Measured versus SPICE model data of IRHF57230 transconductance.

ID (A)	Z Calc (Ω)	Z Meas (Ω)	Difference
0.001	141.5	148.7842	4.90%
0.002	74.43	77.24336	3.64%
0.005	30.86	36.65325	15.81%
0.010	15.69	17.25737	9.08%
0.025	6.47	7.357315	12.06%
0.050	3.35	3.620949	7.48%
0.100	1.77	1.798531	1.59%
0.200	0.975	0.939866	-3.74%
0.500	0.492	0.448749	-9.64%
2.500	0.115	0.126	8.73%
5.000	0.0804	0.088	8.64%
8.200	0.0663	0.066	-0.45%
			4.84%

Table 4. Measured versus SPICE model data of IRHF 57230 transconductance.

ID	Measured		Simulated
Iout	Bandwidth	Phase Margin	Bandwidth	Phase Margin
1 mA	663 Hz	32°	627 Hz	37°
100 mA	9.18 kHz	79°	8.41 kHz	78°
1 A	46 kHz	45°	41 kHz	62°

At the higher bandwidth associated with the 1-A load current, the phase margin is dominated by the equivalent series resistance (ESR) of the output capacitor, which is frequency dependent (Table 4). For better correlation, a polypropylene or ceramic capacitor should be used to minimize the nonlinearity effects of the ESR. Another alternative is to create a nonlinear model for the capacitor ESR as a function of frequency, which has been performed previously.^[4]

The results of these simulations show excellent agreement between the measured and simulated data, validating the new SPICE model. Figs. 6 and 7 illustrate the regulator's step response to a 1-mA to 1-A load change. The results from actual circuit measurements (Fig. 6) correlate closely with those from the SPICE model (Fig. 7). The LDO example highlights the effects of the MOSFET G_FS on the bandwidth of the regulator and the importance of obtaining an accurate model.

The detailed measurement results and other data can be found at www.AENG.com/Articles/MosFet.asp.

References

1. Kielkowski, Ron. SPICE Practical Device Modeling. McGraw-Hill Inc., 1995.

2. SpiceMod. The Spice Modeling Spreadsheet, User's Guide. Intusoft, 1997.

3. Cordonnier, Charles. Spice Model for TMOS Power MOSFETs, AN1043, Motorola Semiconductor Application Note, 1989.

4. Budihardjo, Irwan, Lauritzen, Peter and Mantooth, H. Alan. “Performance Requirements for Power MOSFET Models.” IEEE Transactions on Power Electronics, Vol. 12, No. 1, January 1997.

5. Sandler, Steven M. An Improved SPICE Capacitor Model, www.AENG.com/pub.asp. AEi Systems, 1999.

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