Predictive Control Maximizes Synchronous Rectifier Efficiency

May 1, 2003 12:00 PM
By Steve Mappus, Texas Instruments, Power Supply Control Products, Manchester, N.H.

Using synchronous rectification, optimal components, and a few design tricks, you've reached your goal of, say, 91% power converter efficiency. Not bad, but what if you could gain 4% additional efficiency with little to no added design complexity.

Power supply designers are all too familiar with the fact that the power switches are among the key contributors to overall power loss. For high current applications, this is the reason lower losses afforded from synchronous rectification are preferred over higher conduction losses associated with discrete diodes. Even when synchronous rectification is employed, several MOSFETs are often placed in parallel as the push is made to squeeze every bit of possible efficiency from a design. Although this is the most direct approach to reducing conduction losses within the synchronous rectifier, other contributors also deserve close attention.

In most cases, the second highest power loss is attributed to the body-diode of the synchronous rectifier. Typically, a dead time exists between the turn-off of the main switch and turn-on of the synchronous rectifier. This dead time must be long enough to assure that the two switches are not on simultaneously, resulting in potentially damaging shoot-through currents. The trade-off is that during the dead time, the full output current remains constant by flowing through the internal body-diode of the commutating MOSFET. The longer the dead time, the greater the amount of time the load current flows through the body-diode — and this can negatively affect overall efficiency.

Predictive Gate Drive^™ technology is an innovative digital control-driven technique that optimizes MOSFET turn-on and turn-off delays in synchronous rectifiers. It uses a closed-loop feedback system to detect body-diode conduction and continuously adjusts dead-time delays to minimize the conduction time interval. It's a precision-controlled, cross-conduction algorithm that virtually eliminates body-diode conduction and associated losses, while actively compensating for temperature variations, load-dependent delays and different MOSFET loads.

Depending on operating frequency and output voltage, the Predictive Gate Drive^™ control method can improve overall converter efficiency 2% to 4%, and the MOSFET power dissipation by 20% to 40% over currently available drive techniques.

To understand these technology improvements, you must first consider previous and current technologies used to minimize cross-conduction in synchronous rectifiers.

Previous and Current Technologies

First Generation: Fixed Delay — The first synchronous rectifier controllers had a fixed turn-on delay between the two gate drivers. The advantage of this technique is its simplicity (see Fig. 1). Drawbacks include the need to make the delay times long enough to cover the entire application of the device and the temperature along with lot-to-lot variation of the time delay.

Adding enough fixed delay dead time to avoid cross-conduction results in a non-optimal design. Since the body-diode of the synchronous rectifier conducts during this dead time, the efficiency of this technique varies with different MOSFETs, ambient temperature, and with the lot-to-lot variation of the dead time delay.

Second Generation: Adaptive Delay — To combat the variability of the internal time delays, second-generation controllers used state information from the power stage to control the turn-on of the two gate drivers. Fig. 2 shows this technique, typically called adaptive gate drive technique.

The main advantage of the adaptive technique is the on-the-fly delay adjustment for different MOSFETs and temperature-variable time delays. Disadvantages include the body-diode conduction time intervals caused by delays in the cross-coupling loops and the inability to compensate for the delay to charge the MOSFET gates to the threshold levels. In addition, it's difficult to determine if the synchronous MOSFET channel is off solely by monitoring the switch-node voltage.

Some devices actually add a programmable delay between the turn-off of the synchronous rectifier and the turn-on of the main MOSFET via an external capacitor. This added delay directly affects the power stage efficiency through additional body-diode conduction losses. Because these losses are centralized in the synchronous MOSFET, the stress and temperature rise in this component becomes a major design headache. The adaptive delay control technique has definite advantages over the fixed delay method. However, it's clear that a better control technique is needed for future low-output voltage converters.

Third Generation: Predictive Gate Drive^™ Technique — Rather than sense the switch-node voltage for body-diode conduction and then adjust the delay time accordingly, Predictive Gate Drive^™ technology samples and holds information from the previous switching cycle to “predict” the minimum delay time for the next cycle. It works on the premise that the delay time required for the next switching cycle will be close to the requirements of the previous cycle.

Conversely, the adaptive technique uses the current state information to set the delay times. The feedback loop propagation delays associated with the adaptive technique result in some inherent body-diode conduction, as shown at A and C in Fig. 3, on page 45.

By using a digital control feedback system to detect body-diode conduction, this technology produces the precise timing signals necessary to operate near the threshold of cross-conduction. In fact, when the Predictive Gate Drive^™ algorithm is working optimally, some overlapping should occur below the MOSFET turn-on threshold, between the upper and lower gate drive signals (see Fig. 4).

Two internal feedback loops in the predictive delay controller continuously adjust the turn on delays for the two MOSFET gate drives G1 and G2. Since these loops are controlled internally, they require no external components. Thus, no additional design is needed to take advantage of the higher efficiency offered by this control. As shown in Fig. 5, t_ON,G1 and t_ON,G2 are varied to provide minimum body-diode conduction in the synchronous rectifier, G2, MOSFET. The turn-off delay for G1 and G2, t_OFF,G1 and t_OFF,G2 are fixed by propagation delays internal to the device.

Since the predictive delay controller is implemented using a digital algorithm, the time delays are discrete. The turn-on delays, t_ON,G1 and t_ON,G2, are advanced or reduced by a single step (typically 4 ns) every switching cycle, until the predictive control hones in on the optimal delay time. The process of continually shifting the delay forward and backward each cycle is known as “dithering.” During steady state operation, dithering should occur within an 8 ns (2 delay bits) window.

While normally avoided, cross-conduction occurring below the MOSFET turn-on threshold voltage is actually favorable, contributing toward higher overall efficiency. Using the Predictive Gate Drive^™ technique, the idea of switching right at the cross-conduction boundary becomes feasible. Because the synchronous rectifier body-diode isn't conducting, the P-N junction never becomes fully saturated, making the reverse recovery process much easier. The shortcomings mentioned with first and second-generation control techniques are overcome using Predictive Gate Drive^™ control, but how much improvement can really be expected? The answer requires an understanding of how much power is actually lost in the synchronous rectifier due to body-diode conduction.

Synchronous Rectifiers and Body-Diode Conduction Loss

Fig. 6, on page 47, shows a simplified synchronous buck power stage highlighting the switch-node voltage waveform, labeled point A. Illustrated are the relative effects on the synchronous rectifier due to a fixed-delay drive scheme (constant, preset delays for the turn-off to turn-on intervals), an adaptive delay drive scheme (variable delays based on voltages sensed on the current switching cycle), and the Predictive Gate Drive^™ scheme.

The period shown as channel conduction is the time when the load current is flowing through the synchronous rectifier. During this interval, the synchronous rectifier is subject to conduction loss, regardless of which control technique is used. However, the longer the time spent in body-diode conduction, the less time spent in channel conduction and the lower the efficiency.

For a synchronous rectifier controlled using adaptive delay, the body-diode conduction time can be as long as 120 ns, as shown in A and C of Fig. 3. Predictive Gate Drive^™ technology maximizes efficiency by minimizing this delay time to near zero, thus keeping the load current flowing where it belongs — through the output channel of the conducting MOSFET.

To numerically show the effect of output voltage on synchronous rectifier efficiency gain, you must consider both the channel conduction and body-diode conduction intervals. For example, assume:

V_F = 1V (body-diode forward voltage drop)

V_DS = 0.1V (MOSFET drain-to-source channel voltage)

Therefore, the efficiency within the synchronous rectifier during the channel conduction interval is:

Likewise, the synchronous rectifier efficiency during the body-diode conduction interval is:

Taking several commonly used output voltages as an example, the following synchronous rectifier efficiencies are compared in Table 1. As shown in the table, the voltage drop associated with the synchronous rectifier body-diode results in a greater percentage of the total synchronous rectifier power loss at lower output voltages. It's for this reason that the greatest potential benefit of Predictive Gate Drive^™ technology is gained in low output voltage power converters.

Switching frequency also impacts the advantages of Predictive Gate Drive^™ control. We can best explain this by focusing on the power dissipated within the body-diode during the conduction interval.

Equation 3 shows that as the switching frequency, F_sw, is increased, the power dissipated in the body-diode, P_d, also increases. In addition, as the frequency is increased, the total switching period is decreased. As the switching period gets smaller, the total body-diode conduction interval makes up a greater portion of the total switching period, resulting in more power dissipated within the synchronous rectifier. Since V_F, I_OUT, and F_sw are all constant, the only way to reduce P_d is to reduce the body-diode conduction time, t_BD(Fall) and t_BD(Rise).

Equation 3 can also be expressed as a percent of total output power, P_o.

For V_F equal to 0.8V and a total body-diode conduction time of 120 ns, the graphs in Fig. 7 illustrate the expected overall efficiency improvement of Predictive Gate Drive^™ technology over Adaptive Delay. Fig. 7(a) shows how the benefit of Predictive Gate Drive^™ technology becomes less than 1% at frequencies below 100 kHz. In terms of efficiency benefit only, an overall gain of less than 1% should be considered impractical from a Predictive Gate Drive^™ technology point of view. Fig. 7(b) shows the highest practical efficiency benefits. For instance, a design with a 1.2V output, switching at 500 kHz, should expect a 4% efficiency increase over a similar design using Adaptive Delay control.

The additional efficiency savings in the synchronous rectifier can be used in several ways. Compared to a design using Adaptive Delay control, the efficiency savings may come in the form of reduced power dissipation, translating to lower junction temperature, increased output current for similar operating temperatures, or higher operating frequency translating to smaller power stage components. As an example, the benefits derived from a Predictive Gate Drive^™ controlled synchronous rectifier resulting in a 46% reduction in power dissipation can be seen in Table 2. The Predictive Gate Drive^™ control technique is currently available in several step-down, dc-dc controllers, and high performance synchronous buck driver ICs.

The benefits of this control technique are especially promising in processor power and multiphase, VRM applications, where the efficiency savings could have a cumulative effect due to multiple synchronous buck power stages operated in parallel.

References

1. Mappus, Steve. “UCC27221/2 Predictive Gate Drive^™ FAQs.” Texas Instruments Literature Number SLUA280.

2. Mappus, Steve. “Predictive Gate Drive^™ FAQs.” Texas Instruments Literature Number SLUA285.

3. Mappus, Steve. “Predictive Gate Drive^™ Boosts Synchronous Rectifier Efficiency.” Texas Instruments Literature Number SLUA281.

4. Mappus, Steve. “12V to 1.8V, 20A High-Efficiency Synchronous Buck Converter Using UCC27222 with Predictive Gate Drive^™ Technology User Guide to accommodate UCC27222EVM.” Texas Instruments Literature No. SLUU140.

5. Mappus, Steve. “5V Input, Variable Output Voltage, 20A High-Efficiency Synchronous Buck Converter Using UCC27222 with Predictive Gate Drive^™ Technology User Guide to Accommodate UCC27222EVM-001.” Texas Instruments Literature No. SLUU147.

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