Improving Efficiency in Synchronous Buck Converters

Apr 1, 2004 12:00 PM
By David Morrison, Editor, Power Electronics Technology

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Two S0-8-sized power MOSFETs introduced by Siliconix Inc. combine the low Q_gd values enabled by the company's WFET process technology with the low R_ds(on) values obtained with itsTrenchFET Gen II technology. The Si4368DY and Si7668DP are designed for low-side operation in low-voltage synchronous buck converters, such as those used in notebook PCs, servers, voltage regulator modules (VRMs) and fixed telecom systems. These 30-V rated MOSFETs feature a maximum on-resistance of 3.6 mΩ (at V_GS = 4.5 V and I_D = 22 A) and an R_ds(on)-times-Q_gd figure-of-merit of 23 mΩnC. A typical value of Q_gd is 6.5 nC.

According to the vendor, these on-resistance and figure-of-merit values represent improvements of 25% and 54%, respectively, when compared with competing MOSFETs. These enhancements improve the overall efficiency of synchronous dc-dc converters by approximately 2% in a typical application. In one example, WFET TrenchFET GenII power MOSFETs are used in a 4-phase converter designed to produce 80 A of output at 1.3 V. This converter operates from a 19-V input and switches at 300 kHz per phase. Two high-side MOSFETS and two low-side MOSFETs are employed per phase.

The figure compares the efficiency of this converter built with WFET TrenchFET MOSFETs with that of the same converter built using competing MOSFETs.

WFET technology alters the shape of the MOSFET's trench structure, creating a thicker gate oxide at the bottom of the trench to reduce C_rss and Q_gd without significantly affecting R_ds(on). A thicker bottom oxide alone does not necessarily result in optimum device performance. This is because the gate oxide at the bottom of the trench must overlap with a thinner gate oxide along part of the trench wall to allow current flow in the device. Moreover, this overlap has to account for process variations in both trench and p-body junction depths. The challenge in fabricating this structure is aligning the transition between the thin and thicker gate oxide layers at the bottom of the trench with the P-body/n-epi junction using a technique that is repeatable. By addressing these challenges, Siliconix obtains the optimum performance of the MOSFET structure, while making it density independent.

The process module developed to implement this technology adds a few steps to the conventional process. This includes a LOCOS-grown oxide providing high-quality oxide and a self-aligned arsenic implant for process margin.

Because the WFET technology reduces C_rss, it was originally applied to high-side MOSFETs (Si4390DY or Si7390DP) to reduce switching losses. However, C_rss also causes cross conduction in low-side MOSFETs, so applying WFET technology to these devices can reduce their losses and improve overall converter efficiency.

The Si4368DY and Si7668DP achieve a low Q_gd/Q_gs ratio of 0.37 for improved shoot-through immunity. Previously, the best ratio available from the company's low-side MOSFETs was 0.33.

The maximum gate-threshold voltage for the Si4368DY and Si7668DP is 1.8 V. The Si7668DP is housed in the thermally enhanced PowerPAK SO-8, while the Si4368DY comes in a S0-8 package.

All WFET power MOSFETs are 100% R_g-tested. Samples and production quantities of the WFET TrenchFET Gen II power MOSFETs are available now with lead times of 10 to 12 weeks for larger orders. Unit pricing in 100,000-piece quantities starts at $1.25.

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