DV/DT Immunity Improved in Synchronous Buck Converters

Jul 1, 2005 12:00 PM
By Steve Mappus, Power Supply Control Applications Engineer, Texas Instruments, Manchester, N.H.

Controlling dv/dt-induced turn-on effect can increase overall converter efficiency and MOSFET reliability.

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As nonisolated synchronous buck power converters continue pursuing higher switching frequencies, the key limiting factor has become switching losses in the high-side MOSFET. The faster the high-side MOSFET can transition on and off, the lower the associated switching losses become. However, addressing one problem introduces another. Specifically, the faster the high-side MOSFET is turned on, the more susceptible the low-side synchronous MOSFET becomes to dv/dt-induced turn-on.

Dv/dt turn-on establishes a situation where the synchronous MOSFET can momentarily become turned on, even though the gate-drive signal commands it to be turned off. In a synchronous buck power converter, when the high-side MOSFET is on, the low side must be off. Inadvertently turning on the synchronous MOSFET through dv/dt can result in shoot-through current when the high-side and low-side MOSFETs momentarily conduct simultaneously. In most cases, the converter will operate as expected with little noticeable difference in performance. However, when the applied dv/dt results in a gate voltage that exceeds the MOSFET gate-to-source threshold voltage, the converter's reliability and overall efficiency suffers.

Although the source of the problem resides internally in the MOSFET, there are design steps that can make the synchronous MOSFET less susceptible to dv/dt-induced turn-on. Since each application can vary (high frequency, low voltage, high current, etc.), the solutions for each application are unique and deserve careful consideration.

Fig. 1 shows a low-side MOSFET (off state) of a synchronous buck converter at the moment a positive dv/dt transition appears across the drain-to-source junction. When the high-side switch turns on, the voltage across the drain-to-source of the low-side synchronous MOSFET rapidly increases, producing a fast-change in voltage, dv, within a very short time interval, dt.

The applied dv/dt results in an instantaneous current flow through the charge of the MOSFET parasitic drain-to-gate capacitance (C_GD). For dt/C_GS>>R_G+ R_EXT+R_DRIVER, most of the current through C_GD would ideally flow out of the gate terminal and back through the driver sink resistance as shown in Fig. 1. The current flowing through the internal gate resistance (R_G) produces a spurious voltage spike (V_GS') seen at the MOSFET gate, which can be approximated by this equation:

If V_GS' is less than the turn-on threshold voltage (V_GS(TH)), then the MOSFET will not turn on. Therefore, the design goal should not be to completely eliminate the effect of V_GS' but to minimize it to a maximum value less than V_GS(TH) under all conditions as stated in the following equation:

Note that there are several approaches for satisfying Eq. 2. R_G, C_GD and R_DRIVER are component parameters that the designer has no control over. R_EXT and dv/dt tend to be more easily addressed since they are design-dependant variables. The first step in designing a synchronous buck power stage for maximum dv/dt immunity begins with proper component selection.

Synchronous Rectifier MOSFET Selection

The first intuitive solution might be to select a MOSFET with a higher turn-on threshold voltage. This makes the MOSFET more immune to dv/dt-induced turn-on, as evident in Eq. 2. However, since synchronous rectifier MOSFETs often carry high-load currents at low duty cycle, selecting the lowest on-resistance device is a primary concern. Since MOSFETs with higher turn-on thresholds also have higher associated on-resistance, this is not the best starting point.

MOSFETs suitable for synchronous rectifier applications are sometimes specified as having improved Cdv/dt-induced turn-on immunity. Aside from package type, voltage rating and current rating, MOSFETs are typically selected for their on-resistance and gate-charge characteristics. So, what does it mean to select a device that is robustly designed for dv/dt turn-on immunity?

The natural dv/dt limit of a MOSFET is defined by how much dv/dt can appear across the drain-to-source without inducing a gate-to-source voltage exceeding V_GS(TH). By considering the capacitive divider formed between C_GD and C_GS shown in Fig. 1 (when the MOSFET is out of circuit), the dv/dt-induced gate-to-source voltage can be calculated by this equation:

As long as V_GS<V_GS(TH), the MOSFET will remain off. From Eq. 3, it is obvious that lowering C_GD and increasing C_GS will result in better dv/dt immunity. However, these are nonlinear parameters, internal to the MOSFET that the power supply designer has no control over. Since MOSFETs are selected based upon gate-charge requirements, Eq. 3 can be rewritten as Eq. 4 to establish an expression related to charge, as in Eq. 5, instead of capacitance:

Dividing both sides of Eq. 4 by the right side of the equation gives Eq. 5:

Q_GS(TH) is the gate-to-source charge for 0 V < V_GS < V_GS(TH) and Q_GD is the gate-to-drain charge defined at the Miller plateau shown in Fig. 2.

The expression of Eq. 5 states that the ratio of charge between Q_GD and Q_GS(TH) should be less than 1 to prevent dv/dt-induced turn-on. However, there are two problems with this approach. Synchronous MOSFETs are selected primarily based upon lowest on-resistance, so the Q_GD/Q_GS(TH) criteria should be secondary when conduction losses are considered. Secondly, from Eq. 5 it can be seen that as V_DS increases, Q_GD/Q_GS(TH) also increases. For a synchronous buck converter, V_DS is equal to V_IN when the high-side MOSFET is conducting. Therefore, converters operating from a higher-input voltage become more susceptible to dv/dt-induced turn-on, even when the synchronous MOSFET is selected according to Eq. 5. Nonetheless, from a dv/dt immunity point of view, this a good starting point to keep in mind, especially for low-voltage converters.

MOSFET Driver Selection

Whether the MOSFET gate-drive circuitry is internal to a dc-dc controller or external, such as a stand-alone synchronous buck MOSFET driver IC, there are specific considerations that can improve dv/dt immunity.

Earlier, MOSFET drivers were designed using a complementary bipolar process to deliver the high current required to efficiently switch the power MOSFET. These types of drivers are effective at sourcing high current, but their ability to fully hold the power MOSFET in a low state is limited by their saturation voltage. Some bipolar drive stages can have saturation voltages as high as 0.75 V. For a synchronous MOSFET with an arbitrary threshold voltage of 1.25 V, this would only leave 0.5 V of dv/dt headroom before cross-conduction could begin.

Most modern synchronous MOSFET drive stages use a MOS-only output stage. ICs using MOS-only drive stages overcome the drawbacks of bipolar stages by fully switching the power MOSFET to ground during the off state. This provides an added benefit for the dv/dt problem, but the disadvantage of a MOS-only driver stage is its inability to source high-gate current at low voltage, such as the power MOSFET gate-to-source threshold voltage.

Why sacrifice drive current for better dv/dt immunity? As shown in Fig. 3, a combination bipolar and MOS architecture, such as that provided by the TrueDrive technology from Texas Instruments, offers the benefits of each process.

The bipolar section provides the rated driver current where it is needed most: at the power MOSFET's Miller plateau. The MOS section is placed in parallel with each bipolar device, yielding a lower pull-down impedance for better dv/dt immunity. For driving low on-resistance MOSFETs with low gate-to-source turn-on thresholds, in applications where the possibility of dv/dt turn-on is a concern, a MOS/bipolar drive stage can offer significant performance improvements. When combined with a MOSFET selected according to Eq. 5, this can sometimes be all the dv/dt precaution that is necessary for low-voltage synchronous buck converters.

Gate-Drive Considerations

In addition to MOSFET selection and drive-stage considerations, there are circuit design measures that should be reviewed. One technique is to slow down the turn-on of the high-side MOSFET, effectively increasing the dt component of Eq. 2. The simplest way to achieve this is to place a Schottky diode in parallel with an external gate resistor (Fig. 4). The rising edge (turn-on) of Q1 now can be controlled by R_G1, while the falling edge (turn-off) is unaffected since R_G1 is shorted by D_G1 when the drive stage is sinking current.

Fig. 5 illustrates a synchronous drive stage that uses an external boost circuit to develop the high-side gate drive. Placing a small resistor (R_HI) in series with high-side supply voltage can have the same effect without requiring a parallel diode.

The waveforms shown in Fig. 6 are from a 12-V input, 1.8-V output synchronous buck converter driven by a UCC27223 with an external high-side boost, gate-drive configuration as shown in Fig. 5. With R_HI = 0 Ω and 15 A of load current, G2 has 2.6 V of dv/dt-induced gate voltage when G1 transitions high. When R_HI is changed from 0 Ω to 5.11 Ω, the dv/dt-induced gate voltage on G2 is reduced from 2.6 V to 1.5 V. Fig. 6 highlights the resultant waveforms for each case to show a direct comparison. The G2 dv/dt effect is reduced by 1.1 V, while the rise time of G1 is slowed down by approximately 10 ns.

Slowing down the rising edge of G1 can provide good results at reducing dv/dt-induced turn-on of the synchronous MOSFET. However, as the high-side gate-drive turn-on is slowed down, the switching losses in Q1 are increased. This may be acceptable as long as the savings in power dissipated due to dv/dt-induced shoot-through current is greater than the power dissipated in Q1 from additional switching losses. The exact point of diminishing return will vary between applications and must be carefully evaluated, especially for high-frequency converters where gate-charge and switching losses can have a compounding effect.

For situations in which the additional switching losses taken on by slowing down the rising edge of Q1 are unacceptable, another option may be to level shift the gate drive of G2. In this case, no attempt is made to reduce the dv/dt effect. Rather, by pulling the gate of G2 below ground reference, the dv/dt-induced voltage “bump” still exists but is shifted further below the MOSFET turn-on threshold voltage.

Whereas Figs. 4 and 5 illustrated circuits to modify the high-side gate drive, the circuit shown in Fig. 7 minimizes dv/dt-induced turn-on by modifying the low-side gate drive. The timing diagram in Fig. 7 shows the gate-to-source voltage of Q2 switching between -V_CL and V_G2 - V_CL. The signal from G2 must first be ac-coupled by properly selecting C_G2 according to Eq. 6, where Q_G2 is the total gate charge of Q2, D is the duty cycle, ΔV_CG2 is the amount of allowable ripple voltage across C_G2 and F_SW is the converter switching frequency:

The function of R_GS is to hold the gate low during initial power-up and to provide a path for current to flow through C_G2 when V_G2 is pulled low during the off state of Q2. From the previous example, V_G2 = V_LO = 6.5 V, and selecting a 1-kΩ value for R_GS, limiting the ripple voltage across C_G2 to 10%, and using a value of Q_G2 = 53 nC, C_G2 is calculated as:

Since the dv/dt-induced voltage on G2 was measured as 2.6 V from Fig. 6, a 2.5-V zener diode and a low-voltage BAT54-type Schottky diode can be used for D1 and D2. The clamp voltage (V_CL) can be calculated as the difference between the zener voltage (V_Z) of D1 and the forward voltage drop (V_F) of D2:

The waveforms shown in Fig. 8 were taken from the circuit shown in Fig. 7 with component values calculated from Eqs. 7 and 8. The 2.6-V dv/dt-induced voltage is still present on G2, but only reaches a maximum amplitude of approximately 0.6 V. As expected, the maximum V_GS amplitude of Q2 has now been reduced to 4.48 V. If a 3-V zener diode were used for D1, the dv/dt voltage spike would be completely level shifted below ground reference but the maximum drive amplitude would only be 4 V.

The design tradeoff for the circuit of Fig. 7 is that as the V_GS drive amplitude of Q2 is reduced, the operating characteristics of Q2 are also affected. For a 12-V to 1.8-V converter, the low-side MOSFET is commutating the full-load current, averaged over 1 D. Therefore, the on-resistance of Q2 must be as low as possible. However, as V_GS decreases, R_DS(ON) increases. By referring to the manufacturer's R_DS(ON) versus V_GS curve for a HAT2165 MOSFET, the on-resistance increases by approximately 0.6 mΩ for a 2-V decrease in V_GS from 6.5 V to 4.5 V. Similarly, the total gate charge also decreases from 53 nC to 33 nC, but the resulting efficiency contribution from gate-charge savings is minimal when compared to the added conduction loss taken on from the increase in R_DS(ON).

This tradeoff between MOSFET operating characteristics and gate-drive amplitude can be compensated for by using a gate-drive circuit with adjustable amplitude.

The circuit in Fig. 9 offers the ultimate flexibility in terms of dealing with dv/dt-induced turn-on effect. All of the benefits discussed can be applied without incurring any of the drawbacks. The high-side MOSFET is fully switched with no added external resistance, the low-side MOSFET can be fully level shifted to within the -V_GS limits of the device and the operating characteristics of the low-side MOSFET can be optimized by selecting the appropriate value for V_LO.

The waveforms shown in Fig. 10 were recorded from a power stage driven by a UCC27223 synchronous buck MOSFET driver that uses a dithering technique known as predictive gate drive. By adjusting the external V_LO drive bias to approximately 8.5 V, the amplitude of G2 is corrected to account for the voltage lost due to the level-shifting operation. This technique can offer the greatest benefit to high-frequency, high-current, 12-V synchronous buck applications such as multiphase voltage regulator modules (VRMs).

Key Points for Improving DV/DT Immunity

To summarize, here are five key points listed in order of lowest to highest complexity:

1. Choose a low-side MOSFET with a Q_GD/Q_GS(TH) ratio that is less than 1.

2. Select a combination MOS/bipolar-MOSFET drive stage with minimum pull-down resistance for the low-side MOSFET.

3. Slow down the turn-on of high-side gate drive (tradeoff: switching loss in high-side MOSFET).

4. AC couple and level shift the low-side drive (tradeoff: conduction loss in low-side MOSFET).

5. AC couple and level shift the low-side drive with adjustable drive amplitude to optimize MOSFET R_DS(ON) and gate-charge characteristics.

At the very least, the first and second points should be considered for all synchronous converter applications. For lower-frequency converters, it may be helpful to allow component placeholders in the design schematic to control the rising and falling edges of the high-side gate drive, as highlighted in the third point. Designers should consider the fourth and fifth key points if either they have experienced dv/dt-induced turn-on problems in previous designs or they anticipate possible dv/dt problems due to MOSFETs not selected according to Eq. 5.

In most cases, a power supply designer gives very little forethought to designing a converter that is optimized for dv/dt robustness. And since dv/dt-induced turn-on is a parasitic high-frequency phenomenon, implementing a fix after the fact can be difficult. However, following a few, simple up-front design steps, combined with good layout techniques, can help assure the best possible switching performance from your synchronous buck power stage.

References

1. Balogh, Laszlo. “Design and Application Guide for High Speed MOSFET Gate Drive Circuits,” Power Supply Design Seminar SEM-1400, Topic 2. Texas Instruments Literature No. SLUP169.

2. Wu, Thomas. “CDV/DT Induced Turn-On in Synchronous Buck Regulators,” International Rectifier.

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