What is in this article?:
- GaN Basics: FAQs
- What is the primary advantage of GaN over silicon power transistors?
- How does a GaN’s Gate threshold voltage function?
- What are the important enhanced GaN FET driving Requirements?
- What is most critical about using GaN devices?
Gallium nitride transistors have emerged as a high-performance alternative to silicon-based transistors, thanks to the technology's ability to be made allow smaller device sizes for a given on-resistance and breakdown voltage than silicon.
What are the important enhanced GaN FET driving Requirements?
The three most important parameters are:
- Maximum allowable gate voltage
- Gate threshold voltage
- Body diode voltage drop
The maximum allowable gate-source voltage for an enhanced GaN FET of 6 V is low compared with traditional silicon. The gate voltage is also low compared to most power MOSFETs, but does not suffer from as strong a negative temperature coefficient. And, the body diode forward drop can be a volt higher than comparable silicon MOSFETs.
Because the total Miller charge (QGD) is much lower for an eGaN FET than for a similar on-resistance power MOSFET, it is possible to turn on the device much faster. Too high a dv/dt can reduce efficiency by creating shoot-through during the ‘hard’ switching transition. It would therefore be an advantage to adjust the gate drive pull-up resistance to minimize transition time without inducing other unwanted loss mechanisms. This also allows adjustment of the switch node voltage overshoot and ringing for improved EMI. For eGaN FETs, where the threshold voltage is low, the simplest general solution is to split the gate pull-up and pull-down connections in the driver and allow the insertion of a discrete resistor as needed.
The LM5113, from Texas Instruments, is an example of an eGaN FET optimized half bridge driver that implements bootstrap regulation. Integrated in the undervoltage lockout is an overvoltage clamp that limits bootstrap voltage to 5.2 V ensuring sufficient reliable operation under all circuit conditions. In addition to the clamp, there are separate source and sink pins, >50 V/ns dv/dt capability, matched propagation time, 0.5 Ω pull down, and separate high side and low side inputs to unlock the efficiencies the eGaN FETs enable.
Fig. 3 shows the cascode configuration with a depletion mode HEMT, there are no special requirements for the gate driver since the gate is connected to a standard silicon gate rated at ±20V with threshold around 2V.
Fig. 3 - Transphorm employs a cascode circuit to drive the GaN device. Drain, Gate and Source are similar to a silicon MOSFET’s D, G, and S and K is the Kelvin contact for the gate return.
For the cascode configuration with a depletion mode HEMT, there are no special requirements for the gate driver since the gate is connected to a standard silicon gate rated at +/- 20 volts with threshold around 2 volts.