The threshold of enhancement mode GaN FETs is lower than that of silicon MOSFETs. This is made possible by the almost flat relationship between threshold and temperature along with the very low gate-to-drain capacitance (CGD). The device starts to conduct significant current at 1.6 V, so care must be taken to ensure a low impedance path from gate-to-source when the device needs to be held off during high speed switching in a rectifier function.

The threshold of depletion mode GaN HEMTs ranges from -5 V to -20 V.

What are the important capacitances in a GaN FET?
Besides its low RDS(ON), the lateral structure of the enhanced GaN FET also makes it a very low capacitance device. It can switch hundreds of volts in nanoseconds, giving it multi-megahertz capability. With a lateral structure, CGD comes only from a small corner of the gate and is much lower than the same capacitance in a vertical MOSFET.

Gate-to-source capacitance (CGS) consists of the junction from the gate in channel, and the capacitance of the dielectric between the gate and the field plate. CGS is large compared with CGD, giving GaN FETs good dv/dt immunity, but still small compared with silicon MOSFETs. The drain-to-source capacitance (CDS) is also small, being limited  to the capacitance across the dielectric from the field plate to the drain. Capacitance vs. voltage curves for GaN FETs are similar to those for silicon, except that fir a similar resistance, its capacitance is significantly lower.

Does the GaN FET have a body diode?
The GaN transistor structure is a purely lateral device, without the parasitic bipolar junction common to silcon MOSFETs. Therefore, the enhancement GaN reverse bias or “diode” operation has a different mechanism, but a similar function. With zero bias gate-to-source there is an absence of electrons under the gate region. As the drain voltage decreases, a positive bias on the gate is created relative to the drift region, injecting electrons under the gate. Thus, there are no minority carriers involved in conduction, and thefore no reverse recovery losses. Although QRR is zero, output capacitance (COSS) has to be charged and discharged with every switching cycle. For devices of similar RDS(ON), enhancement GaN FETs have significantly lower COSS than silicon MOSFETs. It takes a bias on the gate greater than the threshold voltage to turn on the enhancement FET in th reverse direction, the forward voltage of the “diode” is higher than silicon transistors.

In the cascode configuration for depletion mode devices, the low voltage silicon MOSFET has very low QRR due to its body diode, which is orders of magnitude lower than a high voltage silicon device with similar ratings to the high voltage HEMT.