Power MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) are three-terminal silicon devices that function by applying a signal to the gate that controls current conduction between source and drain. Their current conduction capabilities are up to several tens of amperes, with breakdown voltage ratings (BVDSS) of 10V to over 1000V. Following are the characteristics associated with power MOSFETs.

Blocking Voltage is the maximum voltage that can be applied to the MOSFET. When driving an inductive load, this includes the applied voltage plus any inductively induced voltage. With inductive loads, the voltage across the MOSFET can actually be twice the applied voltage.

Avalanche Characteristics determine how much energy the MOSFET can withstand under avalanche conditions. Avalanche occurs if the maximum drain-to-source voltage is exceeded and current rushes through the device. The higher the avalanche value, the more rugged the device. The avalanche condition can cause two possible failure modes that can destroy a MOSFET. The most destructive is “bipolar latching” that occurs if the device current causes a voltage drop across its internal device resistance, resulting in transistor action and latching of the parasitic bipolar structure of the MOSFET. A second failure mode is thermal, which occurs if the avalanche condition raises the device temperature above its maximum junction temperature.

Trench technology offers an avalanche capability approaching industry-leading planar technology. To ensure satisfactory performance, devices in this technology can be fully characterized for single pulse avalanche energy (EAS) up to their maximum junction temperature. The higher the EAS, the more rugged the device. Some devices are rated in terms of EAR, the repetitive avalanche energy.

Trench technology provides the desirable characteristics of low on-resistance sometimes at the expense of high avalanche energy. Trench power MOSFET technology provides 15% lower device on-resistance per unit area than existing benchmark planar technologies but usually at the cost of higher charge. And, the trench technology allows 10% lower on-resistance temperature coefficient. Fig. 1 plots single pulse avalanche energy for a MOSFET.

On-Resistance, or RDS(ON), determines the power loss and heating of the power MOSFET. The lower the on-resistance, the lower the device power loss and the cooler it will operate. Low on-resistance drastically reduces heat-sinking requirements in many applications, which lowers parts count and assembly costs. In many applications, the low on-resistance also eliminates the need to parallel MOSFETs for low on-resistance, which leads to improved reliability and lower overall system cost than previous MOSFET generations. In virtually all MOSFETS, the n-channel versions have lower on-resistance than p-channel devices with the same operating voltages. Fig 2 shows the variation of RDS(ON) with junction temperature for VGS = 4.5 V and 10 V. VGS is gate-to-source voltage.

Maximum junction temperature, TJ(max), is a function of the electrical characteristics of the device, as well as the package employed. Package thermal properties determine its ability to extract heat from the die. The junction-to-ambient and junction-to-case thermal resistance is a measure of the MOSFET’s ability to extract heat. Data sheets rate thermal resistance in terms of either °C/W or K/W. The lower the thermal resistance, the more efficient the package is in eliminating heat. In some cases, a heat sink may be required to maintain the device junction temperature below its maximum rating.

Rated Drain Current, ID, reflects the ability of the MOSFET to drive a specific load. When operated in the pulsed mode, the MOSFET’s drain current can be several times its continuous rating. In the pulsed mode the pulse width and duty cycle determine safe drain current and device power dissipation. Fig. 3 shows maximum drain current vs. case temperature.

Safe Operating Area, SOA, is a function of the voltage and current applied to the MOSFET. Power semiconductor manufacturers include a curve in their power transistor data sheets (Fig. 4) that defines the allowable combination of voltage and current, which is called the device’s safe operating area (SOA). If you exceed the SOA, the chip can get too hot and fail.

Gate Charge depends on its gate-to-source capacitance. The lower the gate charge, the easier it is to drive the MOSFET. Total gate charge, QG, affects the highest reliable switching frequency of the MOSFET. The lower the gate charge, the higher the frequency. Operation at higher frequencies allows use of lower value, smaller size capacitors and inductors, which can be significant factors in system size and cost. Some new trench MOSFETs exhibit lower gate charge than some existing planar technologies. Fig. 5 shows the gate charge for a typical power MOSFET, specified in nC, nano-coulombs.

Although input capacitance values are useful, they do not lend themselves to calculation of the gate current required to switch the device in a given time and they do not provide accurate results when comparing the switching performance of two devices. A more useful parameter from the circuit design point of view is the total gate charge. Most manufacturers include both parameters on their data sheets. Using total gate charge, QG, the designer can calculate the amount of current required from the drive circuit to switch the device on in a desired length of time because QG = current x time. For example, a device with a gate charge of 20nC can be turned on in 20msec if a current of 1mA is supplied to the gate, or it can turn on in 20nsec if the gate current is increased to 1A.

Gate charge and on-resistance are inter-related. That is, the lower the gate charge, the higher the on-resistance and vice versa. Historically, MOSFET manufacturers have focused on reducing RDS(on) without paying much attention to gate charge. This has changed in the last several years, with new designs and processes becoming available that offer reduced gate charge devices. The product of RDS(on) x QG is a figure of merit (FOM) that compares different power MOSFETs for use in high frequency applications

MOSFET Threshold Voltage, VGS(th), is the minimum gate-source electrode bias required to form a conducting channel between the source and the drain regions. It is usually measured at a drain-source current of 250 µA. A value of 2V to 4V for high voltage devices with thicker gate oxides, and logic-compatible values of 1V to 2V for lower voltage devices with thinner gate oxides are common. In battery-based applications where power is a premium, the trend is towards lower values of RDS(on) and Vgs(th). Logic level MOSFETs have typical values of about 2V to 3V, whereas other devices can have higher values. Fig. 6 shows the threshold voltage plotted against junction temperature.

MOSFET power losses relate primarily to their use as power switches where operation goes between on and off states. When the MOSFET turns on losses depend on the product of operating current and on-resistance. When off, the losses depend on the product of off-state current and RDS(ON). There are also losses when the MOSFET goes from on to off and vice versa. These losses are affected by its speed when going from on to off and vice versa.

Maximum Allowable Power Dissipation, PD, describes the MOSFET maximum dissipation for the maximum allowable junction temperature, TJ(max). Typically, this rating specifies the case temperature held at 25°C. TJ(max) is normally 150°C or 175°C.

MOSFET thermal impedance, RθJC, is its junction-to-case thermal impedance. A typical surface mount package can have a thermal resistance of 30-50 °C/W, whereas a typical TO-220 device can be 2°C/W or less. Data sheets may also provide a value for RθJA for the junction-to-ambient thermal resistance of the power MOSFET.

Body-Diode Forward Voltage (VSD) is the guaranteed maximum forward drop of the body-drain diode at a specified value of source current. The value of VSD is significant and must be low in applications where the source-drain voltage may extend into the negative range, causing forward biasing the body-drain diode. If this happens, the source-drain current flows from drain straight to the source contacts, across the forward biased body-diode p-n junction.

A second and more dominant current conduction path exists through the channel if the gate-source voltage, VGS >VGS(th). Low voltage and low RDS(on) power MOSFETs are used in such synchronous rectifier modes since their forward voltage drop can be as low as 0.1V versus the typical Schottky diode forward voltage drops of 0.4-0.5V. Maximum values of 1.6V for high voltage devices (>100V) and values of 1.2V for low voltage devices (<100V) are common for VSD. A typical source-drain diode forward voltage is shown in Fig. 7.

Maximum dV/dt is the specified maximum rate of rise of source-drain voltage. If this rate is exceeded, the voltage across the gate-source terminals may become higher than the threshold voltage of the device, forcing the device into current conducting mode and under certain conditions a catastrophic failure may occur.

There are two possible mechanisms by which a dV/dt induced turn-on may take place. One becomes active through the feedback action of the gate-drain capacitance CGD together with CGS forming a capacitive divider that can generate a pulse sufficient to exceed the VGS(th) and turn the device on during fast voltage transitions on the drain. Another is when a voltage ramp appears across the drain and source terminals of the device. Usually the driver will sink a current flowing through the gate resistance, RG, to clamp the gate low during the off state, if RG is too large, it is sometimes possible that the driver is isolated from the gate allowing the device to turn on. RG is the total gate resistance in the circuit.

The second mechanism for the dV/dt turn-on in MOSFETs is through the parasitic BJT. The capacitance associated with the depletion region of the body diode, extending into the drift region is denoted as CDB and appears between the base of the BJT and the drain of the MOSFET. This capacitance gives rise to a current that flows through the base resistance, RG, when a voltage ramp appears across the drain-source terminals.

Static Electricity (ESD) Effects are another way to kill semiconductors. The charge accumulated by a person handling an MOSFET semiconductor is often enough to destroy the part. Therefore, manufacturers of semiconductors have instituted static discharge ratings that range from 3000V to 5000V. Handlers of MOSFET semiconductors use grounding straps and conductive surfaces to prevent static charge problems.

Switching performance of a MOSFET is determined by the time required to establish voltage changes across capacitances and current changes in inductances. RG is the distributed resistance of the gate and is approximately inversely proportional to active area. Values of around 20 Ω-mm2 are common for the product of RG and active area for polysilicon gates. Fig. 8 shows the parasitics in the MOSFET input. LS and LD are source and drain lead inductances and are around a few tens of nH. There are also several parasitic capacitances associated with the power MOSFET. Gate-source capacitance, CGS, is the capacitance due to the overlap of polysilicon gate with the source and the channel regions and is not a strong function of applied voltage. Fig. 9 illustrates the variation of the parasitic capacitances vs. the drain-source voltage.

CRSS is the reverse transfer capacitance, which is the capacitance between the drain and gate with the source connected to ground. This capacitance is equal to the gate-to-drain capacitance. CRSS, often referred to as the Miller capacitance, is one of the major parameters affecting rise and fall times of the output voltage during switching. Plus, it also affects turn-off delay time. The capacitances decrease over a range of increasing drain-source voltage, especially the output and reverse transfer capacitances.

Efficiency is an important criterion in designing dc-dc converters, which means power losses must be minimized. These losses are caused by the power switch, magnetic elements, and the output rectifier. Reduction in power switch and magnetics losses require components that can operate efficiently at high switching frequencies. Output rectifiers can be Schottky diodes, but synchronous rectification (Fig. 10) consisting of power MOSFETS can provide higher efficiency.

MOSFETs exhibit lower forward conduction losses than Schottky diodes. Unlike conventional diodes that are self-commutating, the MOSFETs turn on and off by means of a gate control signal synchronized with converter operation. The major disadvantage of synchronous rectification is the additional complexity and cost associated with the MOSFET devices and associated control electronics. At low output voltages, however, the resulting increase in efficiency more than offsets the cost disadvantage in many applications.

MOSFET Packages

MOSFETs are available in Small Outline IC (SOIC) packages for applications where space is at a premium. Larger through-hole TO-220, TO-247 and the surface mountable D2PAK or SMD-220 are also available. Newer package styles include chip scale devices, DirectFET™, and PolarPak™ packages.

Devices with breakdown voltage ratings of 55V-60V and gate-threshold voltages of 2 to 3V are used mainly in through-hole packages such as TO-220, TO-247 or the surface-mounted D2PAK (SMD220). These through-hole packages have very low thermal resistance. Despite their higher thermal resistances, more surface-mount SOIC packages are finding their way into applications due to the continuous reduction in on-resistance of power MOSFETs. SOIC packages save space and simplify system assembly. The newest generation of power MOSFETs use chip scale and ball grid array packages for low voltage power MOSFETs.

The MOSFET SO-8 package has been used widely for several years, but it impacts electrical and thermal performance. The DPAK solves some SO-8 thermal limitations, but its larger size, package resistance and source inductance, may not suit some applications. In fact, any wire-bonded device, and the SO-8 in particular, has performance limitations:

  • Resistance of internal bonding wires from the drain to package leads increases the MOSFET’s RDS(ON), which increases power dissipation.
  • Inductance of internal wire bonds introduces parasitic inductance on the gate, source and drain terminals, which impacts MOSFET switching speed.

Thermal conductivity of the path from the lead frame’s drain leads to the PCB increases junction-to-PCB thermal impedance and increases MOSFET operating temperature. The source connection can have even higher thermal impedance to the PCB.

Junction-to-case thermal impedance of the plastic-covered standard SO-8 has poor thermal conductivity to the top of the package, which limits device cooling and power handling.

Designed for efficient topside cooling in a SO-8 footprint is International Rectifier’s DirectFET power MOSFET packaging technology (Fig. 11). In combination with improved bottom-side cooling, the new package can be cooled on both sides to cut part count by up to 60%, and board space by as much as 50% compared to devices in standard or enhanced SO-8 packages. This effectively doubles current density (A/in2) at a lower total system cost. The DirectFET MOSFET family offerings match 20V and 30V synchronous buck converter MOSFET chipsets, followed by the addition at 30V targeted for high frequency operation. The DirectFET MOSFET family is also available in three different can sizes.

Thermally Enhanced Package

Vishay’s PolarPAK® (Fig. 12) is a thermally enhanced package that facilitates MOSFET heat removal from an exposed top metal lead-frame connected to a drain surface in addition to a source lead-frame connected to a PCB. PolarPAK was specifically designed for easy handling and mounting onto the PCB with high-speed assembly equipment and thus to enable high assembly yields in mass-volume production. PolarPAK power MOSFETs have the same footprint dimensions of the standard SO-8, dissipate 1°C/W from their top surface and 1°C/W from their bottom surface. This provides a dual heat dissipation path that gives the devices twice the current density of the standard SO-8. With its improved junction-to-ambient thermal impedance, a PolarPAK power MOSFET can either handle more power or operate with a lower junction temperature. A lower junction temperature means a lower RDS(ON), which in turn means higher efficiency. A reduction in junction temperature of just 20 °C can also result in a 2.5 times increase in lifetime reliability.

Texas Instruments’ family of standard-footprint power MOSFETs dissipate heat through the top of the package for high-current DC/DC applications. DualCool™ NexFET™ power MOSFETs provide up to 50 percent more current through the MOSFET and improve thermal management over other standard-footprint packages. Enhanced packaging technology reduces thermal impedance to top of package from 10 degrees to 15 °C/W to 1.2 °C/W, increasing power dissipation capability by up to 80 percent. Efficient dual-side heat sinking enables up to 50 % more current through the FET, giving designers the flexibility to use higher current processors without increasing end equipment size.

Infineon Technologies AG and Fairchild Semiconductor International Inc. have agreed to share compatible their power MOSFET packages, which covers the Infineon PowerStage 3x3 and Fairchild MLP 3x3. This agreement takes advantage of both companies expertise for asymmetric, dual and single MOSFETs for DC-DC applications from 3 to 20A. Fairchild and Infineon have standardized the pin-out and have complementary performance levels, offering two sources for high efficiency design needs.

DrMOS

An approach for configuring a reduced-size, scalable multiphase converter is to apply Intel’s DrMOS™ specification of November 2004. Fig. 13 shows a generic version of a DrMOS module.

A major advantage of using a multi-chip module for a DrMOS device is that the individual MOSFET’s performance characteristics can be optimized, whereas monolithic MOSFETs produce higher on-resistance. However, the component cost of a multi-chip module may be higher than a monolithic equivalent. The designer should view the cost from a system viewpoint. That is, space is saved, potential noise problems are minimized, and fewer components reduce production time and cost.

Unlike discrete solutions whose parasitic elements combined with board layout significantly reduce system efficiency, the DrMOS module is designed to both thermally and electrically minimize parasitic effects and improve overall system efficiency. In operation, the high-side MOSFET is optimized for fast switching while the low-side device is optimized for low RDS(ON). This arrangement ideally accommodates the low-duty-cycle switching requirements needed to convert the 12V bus to supply the processor core.

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