Most hot-swap-control integrated circuits are sophisticated and capable; they relieve the board-level engineer of a great deal of work that used to be associated with designing reliable and robust systems. The designer must still contend with choosing a c
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TYPICAL HIGH-SIDE, n-channel, hot-swap “soft-switch” systems use a charge pump to drive the gate of an external MOSFET above the voltage of the supply being controlled (Fig. 1). When the gate voltage is high, the current flows downstream to the load. This load current is measured as a voltage developed across a known resistance in series with the MOSFET switch. By limiting inrush current through the MOSFET, the system protects the supply's upstream circuitry against overloads and short circuits on the load side.
The circuit in Fig. 1 shows a typical hot-swap or soft-switch circuit with a high-side n-channel MOSFET. This circuit is placed between an always-on power supply and a load. The load may be removable for service, or may require controlled application of power for other reasons, such as energy efficiency or fault isolation.
An integrated-circuit hot-swap controller as shown in the diagram provides a gate-drive potential higher than the supply voltage to enhance the external MOSFET switch. A current-sense amplifier converts the differential voltage across the sense resistor into a single-ended signal that can be compared to one or more overcurrent protection or warning thresholds. The overcurrent comparator discharges the gate of the MOSFET if the load current exceeds the protection threshold, isolating the common supply from a faulty load. This allows other loads connected to the supply to continue operating, even if one or more individual load devices fail.
Other functions that may be integrated in the hot-swap controller are status outputs such as fault or power-good signals, and enable inputs. Additionally, the current-sense signal may be made available to other monitoring devices through a buffered output. Some details of the application circuit may vary, such as placing the current-sense resistor before the MOSFET, or eliminating the sense resistor entirely, but the fundamental principles of operation remain the same as long as an n-channel MOSFET is used for the switching element.
Selection of this external MOSFET switch is critical to the cost, footprint, performance, and reliability of any hot-swap system. The steady-state requirements are straightforward and readily understood, but the dynamic electrical and thermal requirements are less so.
One of the first parameters to be established for a hot-swap system is the voltage range of the supply to be controlled. Most systems have a fairly stable supply voltage, but somesuch as Firewire and telecom applications - must tolerate a wide range of input voltage.
Typical and maximum load currents must also be determined early in the design. Most applications have fixed maximums for load current, but newer controllers (MAX5961 and MAX5967 from Maxim or the ADM1275 from Analog Devices, for instance) let you adjust the maximum current dynamically, using a two-wire serial-communications interface. Because the n-channel pass device chosen for a hot-swap system must obviously withstand the maximum anticipated supply voltage and load current, those parameters make a reasonable starting point in selecting the FET.
Choose a FET whose breakdown voltage (VDS) is adequate for the voltage being controlled, because the full supply voltage will appear across the FET whenever the hot-swap controller shuts down the controlled voltage by pulling the FET's gate to ground. It's wise to incorporate a safety margin in the VDS rating, to allow for overvoltage transients and inductive spikes that may be present at the drain during shutdown. A margin of 20% to 50% is reasonable. More won't hurt, but a higher VDS rating can add cost, size, and gate charge to the FET, all of which harm performance.
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You must ensure that the chosen FET is rated for the maximum gate-drive voltage that will be delivered by the hot-swap controller. Most low-voltage high-side controllers (such as the dual-channel MAX5956) deliver about 5V gate-to-source when fully enhanced, which works well with logic-level n-channel devices. Other hot-swap controllers (such as the MAX5947) may deliver a higher voltage to drive FETs rated for higher-voltage applications. The engineer must ensure that the anticipated gate drive from the controller is sufficient to achieve an optimum on-resistance (RDS(on)), but not so high that it exceeds the maximum rated gate-to-source voltage.
The gate-to-source voltage and on-resistance specified for the FET are closely related. The maximum permissible on-resistance can be quickly established for the hot-swap FET by determining the maximum forward voltage drop (VDROP) that can be tolerated by the load. For example, if the load must receive 12V ±5%, then the total voltage drop incurred by the hot-swap system under normal operating conditions must be less than 5% of 12V, or 600mV.
Note that VDROP must include the voltage drop across the sense resistor, and also the parasitic (copper) losses. The actual drop across the MOSFET must be considerably less than VDROP, to allow for factors such as tolerance in the power-supply regulation, voltage across the current-sensing resistor, and resistive losses in the copper traces and cabling.
For normal operation, the largest voltage drop in the hot-swap system occurs at full load current. Although full load current is less than the intended trip current for the circuit breaker (ICB), the circuit breaker threshold voltage can serve as a worst-case approximation for voltage across the sense resistor. So, to find the maximum permissible RDS(on), subtract the circuit breaker threshold voltage (VCB = ICB × RSENSE) and copper resistive losses VLOSS from VDROP, and then divide this number by the anticipated maximum load current:
If efficiency and power dissipation are critical, consider using a hot-swap controller that can operate without a sense resistor. The MAX5924-MAX5926 controllers, for example, use the on-resistance of the MOSFET itself to monitor load current and provide overcurrent protection. (A “load probe” provides protection before the MOSFET is fully enhanced.) These devices also incorporate temperature compensation to correct for the increase in RDS(ON) as temperature rises, which provides accurate protection across a wide range of load current and ambient temperature.
Steady-state current rating for a MOSFET seems straightforward, but it's not enough to simply check the continuous drain current rating (ID) on the first page of the FET data sheet! For many FETs, the ID values are specified at optimum VGS and at an industry-standard case temperature of just 25°C. In practice, however, the continuous current-handling capability of a power MOSFET is determined by the combination of ambient temperature, maximum operating junction temperature TJ, resistive power dissipation PD in the FET, and its junction-to-ambient thermal resistance RθJA, given in °C/W.
The MOSFET steady-state power dissipation PD is simply the product of the square of the current and the RDS(on) at the hot-swap controller's typical gate-drive voltage. The rise of junction temperature above ambient is the product of PD and RθJA. It's wise to design for worst-case conditions, by using the maximum specified RDS(on) at the hot-swap controller's minimum specified fully-enhanced gate drive.
To find the maximum allowable PD, it's easiest to work backwards from the maximum operating junction temperature, TJ, as specified in the FET data sheet. To find the maximum allowable temperature rise in the FET, you then subtract the anticipated maximum ambient temperature from TJ:
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The maximum allowable power dissipation in the FET is the temperature rise divided by the junction-to-ambient thermal resistance:
Finally, the maximum load current is the square root of maximum power dissipation divided by the MOSFET on-resistance:
For most applications, you should select a FET whose calculated IDS(max) is 20% to 50% higher than the required maximum load current. To ensure that the worst-case continuous current never exceeds IDS(max), you should set the hot-swap controller's circuit-breaker trip point at or below IDS(max), by selecting a current-sense resistor according to:
where VCB(max) is the maximum trip-threshold voltage specified for the circuit breaker, from the hot-swap controller's data sheet. To increase IDS(max), choose a FET with lower RDS(on), lower RθJA, or higher TJ.
Note that RθJA can vary widely with airflow and with the PCB layout and construction. Where two or more thermal- resistance values are specified for a FET, it is important to distinguish between RθJA and the smaller junction-to-case thermal resistance, RθJC. The junction-to-case value is usually relevant only for short-lived transient events, because the heat capacity of the device package is small. For steady-state operation, the larger case-to-ambient thermal resistance is almost always a bottleneck in the thermal design.
Careful board layout and the use of convective or forced-air cooling can greatly reduce an actual RθJA value. For this purpose, the MOSFET data sheet may include valuable recommendations regarding the PCB footprint and heatsink. Many improvements in MOSFET packaging have been introduced in the last few years. Excellent thermal performance is now available with device packages such as International Rectifier's DirectFET, Vishay's PowerPAK, and other thermally-enhanced packages from other power MOSFET suppliers.
Three different operating conditions can subject the MOSFET switch to substantial stress: startup, shutdown, and normal operation. We've already discussed the power dissipation requirements for normal operation, which the FET must be able to sustain indefinitely. Startup and shutdown can impose significantly higher power dissipation on the FET, but we take a different approach to specify the MOSFET for these short-duration conditions.
Two techniques are commonly used to limit inrush current during startup of a hot-swap system. The first controls the output's voltage slew rate (dV/dt), either open-loop or closed-loop. The second actively limits the output current during startup, making the hot-swap system appear to the load as a constant-current source. The MAX5933 (Fig. 2) is an example of a hot-swap controller that employs active current limiting with a “foldback” characteristic to limit MOSFET power dissipation during startup.
Hot-swap controllers for telecommunications (such as the MAX5921 and MAX5939), must contend with large step changes in input voltage. They therefore employ active current-limiting to control the inrush current to load capacitance during these transients. Low-voltage hot-swap controllers that do not have to handle step input changes typically control the MOSFET gate and source dV/dt, thereby providing a simple means for controlling the startup inrush current to load capacitance without incurring a large power-dissipation penalty during a load fault.
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A notable exception to this generalization is the MAX5946, which employs active current-limiting to ensure that expansion card slots never exceed the maximum current specified by the PCI Express™ specification. Similarly, the MAX5943 and MAX5944 mid-voltage controllers are available in versions with and without active current-limiting, to accommodate the wide range of operating conditions permissible in FireWire® ports.
VOLTAGE SLEW-RATE CONTROL
To implement dV/dt control at startup in a high-side n-channel hot-swap system, the gate of the FET is slowly enhanced at constant dV/dt, and when this voltage exceeds the gate threshold, the source rises at the same slew rate. The dV/dt of the gate can be controlled open-loop by driving the gate with a fixed pull-up current. A capacitor between gate and ground then sets a constant gate-voltage slew rate:
IPU = Constant gate-pull-up current
CGATE = Total gate-to-ground capacitance
(In a closed-loop dV/dt control scheme, the FET source voltage is compared to a voltage ramp, and the gate pull-up current is varied to force the source dV/dt to track this ramp.)
Load-inrush current is the product of the FET source dV/dt and the total load capacitance, combined with the any resistive current drawn by the load:
The value of ILOAD during startup is not well-defined, but you can minimize it by holding downstream power supplies and circuits in “reset” until the hot-swap control system asserts a “power good” signal. In many cases the capacitive charging current dominates load current, and constitutes the majority of the total inrush. When using dV/dt to control inrush current, the system designer must assess startup load current and determine whether it can be ignored.
To select an appropriate FET, the designer must estimate the transient power dissipated in the FET during startup. For dV/dt control, current is relatively constant and the voltage drop across the FET ramps down at a fixed rate (as the output ramps up to the input voltage). Because power is the product of voltage and current, we can see that startup power dissipation in the FET is a decreasing triangular pulse, starting at:
The duration of the startup pulse is the time required to charge the load capacitance:
Because the power pulse is triangular in shape, the peak power divided by two yields the equivalent average “square pulse” startup power:
To determine the FET's rise in junction temperature during startup, use the transient thermal impedance chart from the FET data sheet to look up the transient thermal impedance, ZθJA, for a square pulse with duration tSTART. A transient thermal impedance chart for an SO-8 n-channel device is shown in Fig. 3.
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Shown in red on this chart is a hypothetical tSTART = 2ms, and the corresponding transient ZθJA value of 2.1C/W. If the inrush current on a 12V supply is 6A, we have a junction temperature rise above ambient of about 75.6°C.
For startup temperature-rise calculations, the single-pulse thermal-response curve is usually appropriate, with the exception of hot-swap controllers that automatically retry after a fault. For auto-retry, the effective duty cycle is the ratio of startup time to the sum of startup time and retry-time delay:
This duty cycle is then used to select the appropriate thermal response curve. As the duty cycle approaches 1, or as the power pulse-width becomes large, note that the transient thermal impedance ZθJA approaches the steady-state value of RθJA, which was used to determine the temperature rise during normal operation.
If the junction temperature rise during startup is excessive, it may be necessary to reduce inrush current by decreasing dV/dt, or by decreasing the load capacitance. As mentioned before, limiting the load-current contribution to inrush during startup is also helpful. Adding an external heatsink to the FET can help bring the case temperature closer to ambient. The junction-to-case thermal resistance RθJC is usually much lower than RθJA, so establishing a lower case temperature may allow use of the ZθJC chart for junction-to-case transient thermal impedance.
Some cases offer no alternative to a larger FET or a package with lower RθJA. The designer must therefore select a MOSFET whose thermal impedance is sufficiently low that its maximum junction temperature rating is not exceeded.
ACTIVE CURRENT LIMITING
As described before, some hot-swap controllers employ an external current-sense resistance and a closed-loop control system to actively limit current during startup and normal operation. These hot-swap controllers drive the gate of the FET to achieve a fixed maximum voltage drop across the sense resistance, and thereby achieve a constant maximum output current. To protect against fault conditions, the active-current-limit hot-swap controller turns off the FET when voltage across the sense resistor remains at or above the current-limit threshold for a fixed time-out period tFAULT.
The startup thermal analysis for FETs used with these controllers is similar to the analysis for dV/dt control of inrush current. It's actually simpler, because the maximum startup time is known - it equals the controller's specified time-out value for faults.
The maximum current is the current-limit threshold voltage divided by the sense resistance:
Of course, the system must be designed such that tFAULT is greater than tSTART, or the system will never start up!
For a normal startup, we again assume the triangular power pulse is equivalent to a square pulse of duration less than or equal to tFAULT, and magnitude ½(VIN × ILIMIT). The thermal analysis then proceeds as described for dV/dt control.
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Thermal analysis during a FET turn-off other than a fault can be considered as the reverse of the startup condition, but the duration of the turn-off event is determined differently. As the hot-swap controller pulls down on the gate of the FET with a known pull-down current, the source slews down from VIN to ground at a rate determined by the pull-down current and the gate capacitance:
This also means that the FET's drain-to-source voltage slews up to VIN at the same rate. The time required to turn off the FET is the gate charge (including added capacitance) divided by the pull-down current:
A worst-case assumption is that ILOAD, max continues to flow through the FET during this time. We then analyze turn-off power dissipation in the FET as equivalent to a square power pulse of magnitude ½(VIN × ILOAD) and duration tOFF. The transient thermal impedance chart can then be used to determine the FET junction rise during the turn-off event, in the same manner as was done for startup.
SHORT-CIRCUIT FAULT CONDITIONS
A hot-swap controller can take one of two actions in the event of a short-circuited load or other overcurrent event. Some hot-swap controllers function as electronic circuit breakers, pulling the gate of the FET to ground after a finite response time. Other controllers control the FET gate voltage to maintain a fixed voltage across a current-sense resistor, making the hot-swap output appear as a current source for a finite time before disconnecting the load by pulling the gate to ground.
Of these two fault-protection schemes, active current-limiting places more stress on the FET, particularly in the event of a low-resistance short circuit of the load. When that occurs, the entire input voltage appears across the FET, and current is fixed at the current-limit value (i.e., set by the sense threshold and sense resistance).
Hot-swap controllers that function as electronic circuit breakers allow higher peak currents during a fault, but power dissipation in the FET is generally less, because the FET gate remains fully enhanced until the fault timer expires. At that time the gate is pulled quickly to ground, which minimizes the width of the switching power pulse.
For hot-swap controllers that employ active-current-limiting fault protection, the hot-swap FET must withstand power pulses with duration tFAULT and magnitude VIN × ILIMIT. The designer should set ILIMIT as close to the anticipated full-load current as possible. A margin of 5% to 10% is adequate for “well behaved” loads, but to accommodate fast load transients without invoking active current limiting, other systems may require margins as high as 50% to 100%.
The value of tFAULT is usually programmable. It should be set as short as possible, but large enough for the hot-swap system to “ride through” spurious overcurrent transients. The value of tFAULT is tied to the startup timer in some active-current-limiting controllers, so its value must also be sized to allow successful startup, as described earlier.
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After selecting a suitable value of tFAULT, you can determine the temperature rise of the FET for a worst-case “zero-Ohm” short-circuit, which applies to the MOSFET a square power pulse of magnitude VIN × ILIMIT and duration tFAULT. To determine worst-case power, be sure to use the maximum value of current-limit threshold and the minimum tolerance on the sense resistance.
Alternatively, you can determine the maximum allowable rise in junction temperature (in °C) and divide it by the pulse power magnitude VIN × ILIMIT to find the minimum acceptable value of ZθJA. That value can then be found on the y-axis of the transient thermal impedance chart, followed horizontally to the single-pulse response curve, and then down to the maximum allowable value of tFAULT.
ELECTRONIC CIRCUIT BREAKER
Hot-swap controllers that function as electronic circuit breakers typically ignore a fault condition (defined as current exceeding the trip threshold of the circuit breaker) for a finite response time tRESPONSE. If the fault persists longer than the response time, the gate of the external FET is pulled quickly to ground. Before the FET turns off, however, the current ISHORT is limited only by RDS(on) of the FET, the sense resistance, and the resistance of the short itself:
For worst-case analysis, we assume a perfect (zero-Ohm) load short, RSENSE at minimum tolerance, and minimum specified RDS(on).
The rise in the FET's junction temperature is determined in the usual manner, for a square power pulse of magnitude ISHORT2 × RDS(on) and duration tRESPONSE. This method determines the thermal response for an extremely severe fault. Most failures exhibit a short-circuited load resistance of several hundred milliohms. Also, if the upstream power supply is capable of delivering only a maximum output current IMAX, then that value can be used to determine short-circuit power dissipation in the FET:
What about a string of events? Assume that the hot-swap circuit starts up for time tSTART, then immediately encounters a short-circuited load when the load is released from “reset” by a power-good signal. The current-limiting hot-swap controller holds the load current at ILIMIT for tFAULT, then pulls down on the FET gate, disconnecting the load during the interval tOFF. In Fig. 4, PD1 is the FET maximum inrush dissipation VIN × IINRUSH, PD2 is the normal operating dissipation ILOAD2 × RDS(on), and PD3 is the short-circuit dissipation ILIMIT ×VIN. This waveform can be approximated as a rectangular duration pulse:
The total energy E dissipated in the FET is the time integral of power, which can be graphically approximated as:
The average power is then (E/tTOTAL), which can be used to look up the transient thermal impedance.
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