SoC Uses Powerline Communications to Control Embedded Applications

Jun 1, 2010 12:00 PM
SAM DAVIS, Editor-in-Chief, PET

At first glance, powerlines would appear to be a potential communications medium for command and control of external devices. This application is complicated because it is difficult to predict the quality and reliability of communications over existing powerlines because of the associated variables of noise, impedance and line quality. The Cypress Semiconductor Corporation's PLC (powerline communication) system, however, has overcome these operating conditions with a design that enables secure and reliable communications up to 11,500 feet.

As shown in Figure 1, a typical Cypress SoC consists of two subsystems on a chip: the PLC Core and PSoC® Core (programmable system-on-a-chip). Apart from the PLC SoC, there is an external Powerline Coupling Circuit that completes the required system hardware. The PSoC Core leverages the programmable analog and digital resources. The PLC core integrates the Powerline MODEM PHY and the Network Protocol. The PSoC core integrates multiple functions beyond communication, such as power measurement, system management and LCD drive. Besides its flexibility and integration, this system offers reliability with 100% powerline data transmission success rates on standard networks and offers retries built into its coding in case data is dropped on noisy or low impedance networks.”

The system offers the flexibility to communicate over high-voltage and low-voltage powerlines for lighting and industrial control, home automation, automatic meter reading and smart energy management (Figure 2) applications.

PLC CORE

Adding the PLC Core to the Cypress SoC inserts the application coding obtained from the programmable analog and digital blocks and microcontroller of the PSoC architecture. This combination provides a single hardware platform for multiple applications, reducing BOM cost, board size and chip count while improving manufacturability. Included are:

• Powerline modem (PHY) physical layer - based on Frequency Shift Keying (FSK) modulation
• Configurable baud rates up to 2400 bps
• Configurable Tx, Rx gains and Band In Use (BIU) threshold
• Powerline optimized network protocol
• Integrated data link, transport, and network layers
• Bidirectional half duplex communication
• 8-bit CRC error detection to minimize data loss
• SPI, UART and I2C enabled powerline application layer

In the physical layer (PHY) shown in Figure 3, the digital transmitter serializes digital data from the network layer and feeds it to the modulator input. The modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic “1” or low level logic “0”. It then generates a square wave at 133.3 kHz (logic “0”) or 131.8 kHz (logic “1”), which is then fed to the programmable gain amplifier to generate FSK modulated signals that are applied to the Powerline Coupling Circuit. This enables tunable amplification of the signal. Using this amplifier, the amplitude of the signal coming out of the chip can be varied between 55 mV to 3.5V. This feature enables the PLC modem to communicate effectively even when the channel is noisy. The logic “1” frequency can also be configured as 130.4 kHz for wider FSK deviation.

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