Fig. 1.     The TPS53915 is a synchronous buck converter that features programmability and fault reporting via PMBus™, which interfaces with the SDA, SDL and image pins.

Texas Instruments’ TPS53915 (Fig. 1), can supply up to 12 A output that is adjustable from 0.6 V to 5.5 V. Its input voltage ranges from 1.5 V to 18 V. A 4.5 V to 25 V VDD input powers an internal 5 V LDO that supports internal functions. Other features are auto-skip mode operation, internal soft-start control, and no requirement for compensation. A forced continuous conduction mode helps meet tight voltage regulation accuracy requirements for performance DSPs and FPGAs. A default switching frequency (fSW) pre-set to 400 kHz can be changed to 1 MHz under PMBus control.  Available in a 28-pin QFN package, the TPS53915 is specified for operation from –40 °C to 85 °C ambient temperature.

 

TPS53915’s D-CAP3 mode control combined with adaptive on-time architecture, results in low-duty-ratio and ultra-fast load-step-response.  Adaptive on-time control tracks and controls the preset switching frequency over a wide range of input and output voltage while increasing switching frequency as needed during a load-step transient. This control scheme does not require an external phase-compensation network, which enables a low external component count. Fig. 2 shows a simplified buck converter using the D-CAP3 mode control architecture.

Fig. 2.     Simplified small-signal loop analysis of the TPS53915’s D-CAP3 mode control.

This proprietary mode control architecture includes an internal ripple generation network that enables use of very low-ESR output capacitors, typically ceramic types. The ripple generation network emulates the ripple component of the inductor current information and then combines it with the voltage feedback signal to regulate loop operation. D-CAP3 control architecture does not require an external current sensing network or voltage compensators.

D-CAP3 control without external compensation has a minimum and/or maximum range of the output filter it can support. An output filter used with the TPS53915 is a low-pass, double-pole L-C type. At low frequencies, the output setpoint resistor divider network and the internal gain of the TPS53915 set the overall loop gain. At the output filter frequency, the gain rolls off at a –40 dB per decade and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and increases the phase to 90 degrees, one decade above the zero frequency.

The inductor and capacitor in the output filter must locate the double pole close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero provides adequate phase margin for its stability requirement. After identifying the application requirements, you should design the output inductance so that the inductor peak-to-peak ripple current is approximately between 25% and 35% of the ICC(max)  (peak current) in the application.