Although the development of power MOSFETs began with the V-MOS structure, the first commercially successful devices were based on the DMOS structure. In the DMOSFET structure, the MOS channel is formed on the surface by using the double-diffusion process with the channel length controlled by the relative diffusion depth of the p-base and n+ source regions. A more heavily doped p+ region is added to the structure to suppress the turn-on of the parasitic npn transistor that is inherent in the MOSFET structure.

The resistance in the path between the drain and source contains many components: The most important ones consist of the drift region, the JFET region, the accumulation region, and the channel region. In addition, for low-voltage (<30V rated) devices, the contributions from the Ohmic contacts and the n+ substrate cannot be neglected. Analysis of the distribution of the resistances within the DMOSFET structure indicates that the channel contribution is dominant due to the relatively low channel density in the DMOSFET structure.

To reduce the on-resistance, the power MOSFET industry shifted to a trench-gate technology about five years ago. In the trench-gate structure, which is also commonly referred to as the UMOSFET structure, the channel is formed on the vertical sidewalls of a trench etched into the silicon surface. Because the drain-source current is directed along a vertical path, the JFET resistance is eliminated. This allows reduction of the on-resistance, not only by removal of one of the resistance components, but also by allowing a smaller cell size, which increases the channel density. Unfortunately, the trench-gate process is more complex and expensive when compared with the planar DMOS process.

In addition, the industry has had to deal with reliability problems associated with high electric fields at the trench corners, which must be solved by rounding the trench corners and buffering the electric field using p+ regions. Furthermore, the extension of the gate into the drift region increases the coupling between the drain and the gate leading to higher “Miller capacitance” and gate charge, which can adversely impact switching performance.

At Silicon Semiconductor, we have re-engineered the planar power MOSFET structure to achieve performance metrics superior to those of state-of-art trench-gate devices. By retaining a planar architecture, the fabrication process remains compatible with mainstream CMOS process lines, and reliability issues are ameliorated. In addition, this architecture has allowed implementation of a silicided gate stack to reduce the internal gate resistance of the MOSFET.

The SSCFET structure contains a deep p+ region that is self-aligned to the gate region. Its higher doping concentration and deeper extension in both the vertical and lateral directions are used to create a potential barrier in the transition-region, which is located below the gate region. The gate width and transition region doping profile are optimized to obtain enhanced power MOSFET performance. The screening of the gate region from the drain potential allows shortening of the channel length, without fear of reach-through-induced breakdown, to reduce its resistance contribution. The channel contribution decreases to half that observed in typical DMOSFETs, enabling specific on-resistances for SSCFETs to approach those obtained in typical trench MOSFETs.

The screening of the gate from the drain potential drastically reduces the Miller capacitance in the SSCFETs with typical values of Crss under 20 pF at a drain bias of 16V for a device with input capacitance Ciss of 3000 pF. The ratio of [Crss/Ciss] for the SSCFET is typically less than 0.01 — an order of magnitude better than for typical trench MOSFETs. Plus, it allows a significant reduction of gate charge. The reduced gate drive currents for SSCFETs places a smaller burden on controllers, enabling migration to higher operating frequency. Furthermore, we have taken the approach of integrating a Schottky diode into the power MOSFET cell structure to create a new device named the Junction Barrier Controlled Schottky Field Effect Transistor (JBSFET). The resulting SSCFETs and JBSFETs provide optimum power switches, as control FETs and sync FETs in dc-dc converters for high-frequency (200 kHz to over 1MHz) voltage-regulator applications, to enhance the efficiency by 2% to 8% while reducing the power device footprint by 200% to 300%.