Noise management, induced by digital circuits on a p. c. board assembly, deserves the attention of power supply designers and those mastering digital, analog, and mixed-mode application problems beyond the confines of the power supply itself. You can effectively control internally generated noise from digital switching with a number of circuit arrangements. SPICE simulations made on a logic gate model gauged the ability of the circuit arrangement to control noise.

An understanding of the nonideal characteristics of the components is essential to make power supply decoupling effective — especially as digital edge transition times decrease, with increased system bandwidth. High speed digital switching involves the rapid transfer of current from the power supply to loads formed by analog or digital circuits.

Digital signal transitions are associated with charge movements through digital systems. Power supply decoupling suppresses the unwanted transients that are otherwise generated by digital switching circuits at their dc supply connections. This noise management is normally provided at the component and the system level of a design. Local decoupling arrangements should be the foundation of the system-level layer of power supply decoupling.


The aim of dc power supply decoupling is to devise a low impedance path between the point in the supply system where a logic element draws the current needed to operate and its local ground contact, forming the return path for current to the power supply.

An electric model is useful to analyze a circuit arrangement for noise control and other problems. Model simulations allow designers to observe circuit modification effects with the benefit of executing experiments quickly, while providing designers insights into the expected behavior of a working system [1,2] .

Some engineers argue that simulations are inaccurate and hinder design. Simulation results are a reflection of the effort to develop accurate circuit models for the elements in the simulated circuit. It's necessary to base these models on the data extracted from real components and measure them with appropriate electrical instruments and techniques. We recommend simulations and “critical circuit” prototypes for testing out new design ideas before committing them to production.

SPICE and related software packages can help to rapidly execute most simulations. Analysis reached through the use of these software packages is repeatable and indicates sensitivities of circuit behavior with respect to components, values, and arrangement.

Decoupling Fundamentals

The TTL-compatible inverting gate in the Advanced CMOS logic family, the 74ACT04, is the basis of the study. You can base a SPICE model on this inverter's detailed datasheet. The next step investigated common decoupling solutions, using simulations of models in the time and frequency domains to demonstrate their impact on the inverter's switching noise.

Placing a capacitor very close to the IC power and ground pin connections takes RF energy generated by rapid changes of current demand on the power supply during switching, and then channels it to the ground return path. This prevents power line channeled noise from subverting normal circuit operation. Uncontrolled power supply noise has many effects on a digital system. Those problems include intermodulation and crosstalk.

The ideal capacitor's reactance decreases with frequency. Examination of the two manufacturers' datasheets indicates the suitability of a particular capacitor for a given decoupling problem. Verify that the speed the capacitor can compensate for voltage changes associated with switching events is commensurate with these transitions.


Several companies produce components for power supply decoupling and noise control use. Nichicon produces through-hole and surface-mount (SMT) aluminum electrolytic capacitors ranging from a few to thousands of μF in their PL series [5] . Murata makes SMT chip capacitors that you can model as lumped element networks or with scattering S-parameter matrices. The Murata Chip Capacitor S-Parameter and Impedance Library, which you can access using their software package, MCSIL, invokes the lumped element model used in some simulations. You can download this software from Murata's Web site [6] .

Nonideal behavior is associated with the capacitor's equivalent series resistance and inductance (ESR and ESL). These parameters are mostly influenced by the capacitor's internal structure, and the need to bring the “plates” (physical locations where the charge is stored) out to wires where connections are afforded. The ambient temperature and to a lesser extent by humidity influence the ESL, ESR, and the self-capacitance, i.e., the amount of useful charge storage capability.

Capacitors exhibit resonance at some point in a swept-frequency test, due to inductance and resistance. This is the frequency at which the overall reactance of the capacitor “inverts” and becomes inductive in nature, the opposite sort of behavior expected. Operating a capacitor beyond its self-resonant frequency serves no useful purpose in power supply decoupling.

Ceramic surface mount capacitors are small components with a finer structure than electrolytic parts. The dielectric is solid, and is made with differing dielectrics and varying temperature characteristics. They have smaller package parasitics and self-resonant frequencies of 10 MHz to 100 MHz.

It's important to base a good decoupling capacitor selection on the RF energy of the switching located in the frequency spectrum relative to the self-resonant frequency of the decoupling capacitor. This also applies to ferrites, which exhibit a similar kind of reactance inversion. A number of parallel-connected capacitors, with differing self-resonant frequencies, provide good decoupling action. This may increase procurement costs that could be significant when accounting for the ICs on a given board. In very demanding VHF and UHF noise control applications, a series ferrite is combined in a Π or T circuit with suitable capacitors to achieve enhanced decoupling performance at somewhat higher cost than a single capacitor.

A good board design incorporates redundant land patterns for connecting decoupling networks to critical power supply and ground nodes in locations as close as possible to the ICs.

SPICE Simulation of the Simple Gate Circuit

We reviewed several different decoupling arrangements using the SPICE simulation technique. Reviewers devised a model of an individual 74ACT04 inverter on the basis of a simplified switch-resistor topology and calculated typical data on the basis of the theory outlined in [7] , and reviewed reference-derived models of the pin interconnects [8] . We used time and frequency domain analyses in identical formats to observe the effects of using different decoupling components on the same gate. Table 1, on page 24, lists five of the simulations.

The schematic for decup0 shown in Fig. 1, on page 24, shows the switch model for the inverter. This model comprises two voltage-controlled switches S1, S2 and resistors R1, R2. The package lead inductance for power, output, and ground returns are modeled as lumped elements L_PWR_PIN, L_OUT_PIN, and L_GND_PIN. The 100Ω, 100 ps delay-time lossless transmission lines T1 and T2 are supposed to represent the tracks routing dc current to and from the gate. If this strip-line, modeled by the T1 and T2 sections, ran over FR-4 material it would be about ½-in. long, giving a power supply lead length of 1 in. total if the ground return is included. The excitation is a 3.2V peak-peak, 4.5 ns transition time pulse running at 20 MHz, and the gate is powered at 5Vdc. This same model is used in all the simulations. The gate is loaded with a 50-pF capacitance.

Rise and fall times of the gate were simulated to be 2.93 ns and 1.55 ns, respectively, in the decup0 simulations. The measured characteristics are typically 4.7 ns for rise time and 2.9 ns for fall time [9] . You can refine the model to account for this.

Looking at the time domain waveforms, note that the local input and output pulse waveforms have a switching transient imposed on them, shown in Fig. 2, on page 26. This transient also shows up on the dc supply and local ground pins of the gate, as shown in Fig. 3, on page 26. These last two waveforms have opposite phases to each other. There's also a periodic, pulsed sinusoid with a period of 400 ps (at a frequency of 2.5 GHz) which is much weaker than the inductive glitches seen at the CNODE and LOCALGND nodes in the simulated network. These pulsed sinewaves appear as thick lines on the plot of Fig. 3 in three time intervals: 12.5 -37 ns, and then repeated 50 ns and 100 ns later. The FFT plot for the supply pin artifacts in Fig. 4, on page 28, clearly shows the correct dc term at 20. log10 (5)≈14 dB and the 2.5 GHz spur, some 61 dB below it. This spur indicates that the power and ground leads resonate periodically, albeit weakly.

The large 1V pk-pk transients on the local power and ground pins are associated with the charge switched into and out of the 50 pF capacitive load through the parasitic inductance of the IC package pins. If you view the load current I(C1) alongside the voltage at the LOCALGND node, as shown in Fig. 5, you can see that V(LOCALGND) is a scaled derivative of the current. It's related as V= -L di/dt, due to the inductance of the ground lead during current inrush from the supply to ground through TGATE when it is ON. A large negative spike occurs when turning the BGATE switch ON.

You can see a close-in view of the power pin artifacts FFT for the signals on the dc supply pin in Fig. 6 out to 500 MHz. The harmonics are uniformly spaced at the data rate of 20 MHz. A spurious maximum of -24.4 dB is recorded.

Aluminum Electrolytic

Nichicon modeled a capacitor in accordance with the datasheet's part. Fig. 7 indicates that the self-resonance of the 220 μF part occurs at about 25 kHz. The component will not control discrete spurious energy at 20 MHz intervals in the frequency spectrum, because the capacitor becomes inductive at frequencies beyond 20 MHz. You can see additional distortion in the output waveform's leading edges, along with the damped ringing of the rising edges. The transients on the power and ground pins are a little different from those of the “decup0” control simulation due to the ESL for this capacitor. Spurs as high as -24.7 dB were simulated. Although this component has plenty of capacitance, its parasitic elements work against it for this kind of decoupling duty — despite the component's capacitance.

SMT 0.1 μF Capacitor

Self-resonance in this component occurs at 30 MHz (Fig. 8), which indicates that it will have some beneficial decoupling effects at this frequency. The input and output waveforms are undistorted and the peak-to-peak voltage on the local ground and power pins is only 25 mV. The spectrum shows spurious noise at a maximum of only -62 dB, which is 38 dB lower than the maximum spurious noise in the control simulation.

SMT 82 pF Capacitor

The next simulation employed the 82 pF 0805 SMT capacitor. This has a higher self-resonance than its 0.1 μF cousin, which occurs at just under 600 MHz, as shown in Fig. 9, on page 37. The capacitor has significant reactance below 600 MHz and doesn't suppress noise as well as a 0.1 μF capacitor in the frequency spectrum. There's ringing on the output voltage waveform at around 100 MHz, due to the local power supply and ground nodes being disturbed by this slow settling transient as you can see in Fig. 10. The DC-500 MHz FFT of the power pin signal shows that there's much higher level of noise. The peak-to-peak noise voltage on the local supply pin is 1.06V pk-pk, which is the worst recorded noise thus far as seen in Fig. 11. Although this capacitor doesn't suppress noise in this application, it does have beneficial effects at higher frequencies.

LC Filter Topology

The schematic in Fig. 12, on page 38, shows how the blocking action of a ferrite in a LC Filter complements a single capacitor. The ferrite has its own self-resonant frequency, which stands at roughly 400 MHz. You can see the ferrite's frequency characteristic in Fig. 13, on page 38. The capacitor and ferrite components work together, along with the parasitic pin inductance, to good effect as a T filter. This filter has two poles and a -40 dB/dec attenuation rate, a characteristic you can see in Fig. 14 beyond the 20 MHz break frequency. The output waveforms manifest the excellent noise control, as shown in Fig. 15.

Practical Concerns

Because different capacitors have better noise control characteristics at differing frequencies, designers often connect differently valued decoupling capacitors in parallel.

The digital gate model is simplistic. It's possible to use more sophisticated topologies, based on data extracted from layouts of IC-based transistors and their parasitic elements. Although the model used was a simple one, it was sufficient in showing how fast switching, internal to a single gate in an IC connected to the power supply, induces noise on the lines carrying current to the gate.

Sensitivity of various arrangements to temperature and component tolerances requires investigation. Many works investigate the robustness of design solutions using statistical measures against such variations. (One example is reference [11] .) Some simulators support the Monte Carlo method as a means of investigating the effect of component variations on performance parameters. Using a lossy transmission line model for the power line and return is worth considering — particularly when running longer feeds over the board assembly.


  1. “Spice Practical Device Modeling,” R. Kielkowski, McGraw-Hill 1995.

  2. “The Spice Book,” Andrei Vladimirescu, J. Wiley & Sons Inc 1994.

  3. “TopSpice® Mixed-Mode Circuit Simulator Reference,” Rev 5.8, Penzar Development Corporation 1999.

  4. “74AC04, 74ACT04 Hex Inverter,” Fairchild Semiconductor, Rev Nov. 1999.

  5. “PL series Extremely Low Impedance, High Reliability Aluminum Electrolytic Capacitors,” Nichicon Datasheet reference CAT.8100P.

  6. “MCSIL download” is located at

  7. “High Speed Digital Design — A Handbook of Black Magic,” H. Johnson and M. Graham, Prentice Hall, 1993.

  8. “Design Innovations Address Advanced CMOS Logic Noise,” Fairchild Semiconductor App. Note AN-690, 1999.

  9. “FACT Descriptions and Family Characteristics,” Fairchild Semiconductor MS010158 Rev Jan. 2000.

  10. “RF Circuit Design” C Bowick, Newnes imprint 1997.

  11. “Tolerance Design of Electronic Circuits,” R. Spence, R. Singh ISBN 0-201-18242-4, Addison Wesley.

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