QUESTION: If PDN (Power Distribution Network) analysis is an assessment of the input power supply voltage to a CPU then why is it measured using a VNA and not an oscilloscope?

ANSWER: First, your understanding of PDN is largely correct.  The PDN includes the voltage regulator, printed circuit board traces or planes, vias and decoupling capacitors including the capacitor series resistance (ESR) and inductance (ESL).  The voltage arrives at the load (CPU) and must be within allowable regulation limits.  Internal to the CPU, the bond wires and die capacitance also form part of the PDN.

While CPUs can be difficult to assess from the PDN perspective FPGAs can be as or even more difficult due to the higher edge speeds.  The spectral content of many high speed FPGAs can be as high as 10GHz, requiring the PDN assessment to include the content from DC to 10GHz. It is clear that only computing the DC input voltage regulation range is insufficient.

Since we are interested in monitoring the voltage at the output of the regulator but including all of the pathways to the pins of the load (CPU or FPGA) it would seem that the best tool would be the oscilloscope, which allows us to directly view the voltage in the time domain. However, a fundamental limitation is that we do not know the load current pattern, since that is determined in large part by the software contained within the CPU or FPGA. It may not be obvious, but the output voltage is a function of the load profile and its reflection through the AC impedance to the regulation to a large degree. Therefore, capturing the voltage excursions of interest requires coordination with the FPGA operation. A resistive PDN and associated load pattern is shown in Figure 1. The same load pattern applied to a PDN with a single anti resonance, caused by the load impedance, is shown in Figure 2.

Figure 1. Load current patter (green trace) and voltage response (yellow trace) for a resistive PDN.


While there is nothing particularly notable in Figure 1, the response shown in Figure 2 indicates two distinctively different responses. The first, natural response results in a damped ringing due to an underdamped antiresonance. The second or forced response is related to the current burst in the center of the load current pattern.

The natural response is the response of the regulator to a load step where by the output voltage is allowed to settle before then next load transient is applied. The forced response is when the load step is applied sometime before the output response has had time to settle. In that case, subsequent load transients can reinforce themselves creating output voltage excursions that are greater than the natural response produces. The behavior is a function of the bandwidth of the regulator.

Therefore, if the regulator’s bandwidth is very close to, or a multiple of, the antiresonant (peak in the AC impedance, See Figure 6) frequency the result can be a growing output voltage waveform. The amplitude of this response will eventually settle to a fixed level after a number of cycles, dependent on the antiresonant Q. Many antiresonances can occur in the PDN range of DC - 10GHz, with each antiresonance exhibiting these interactions with the regulator and load step profile.

Figure 2. Load current patter (green trace) and voltage response (yellow trace) for a PDN with a single resonance.