Chandra said the higher levels of integration and higher power density on today's chips are causing heat and temperature gradient problems that are not addressed by current methodologies.

“Existing design tools typically use a constant temperature methodology and attempt to account for temperature variations by considering a large number of statistical temperature points,” he explained. “This approach is flawed, first because each data point assumes a constant on-chip temperature--and that is no longer a reasonable assumption with small geometries--and also because the statistical distribution is usually aimed at worst-case situations, which inhibits design optimization due to the large design margins needed in such situations.”

As a result, Chandra said, it’s possible to miss temperature-related design violations. Gradient’s thermal analysis engine is said to provide a 3-D full-chip temperature map to account for the electrical effects of thermal gradients within a semiconductor.